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6069a?atarm?05/04 features arm7tdmi ? arm ? thumb ? processor core ? in-circuit emulator, 36 mhz operation ethernet bridge ? dual ethernet 10/100 mbps mac interface ? 16-kbyte frame buffer 1 k-byte boot rom, embedding a boot program ? enable application download from dataflash ? external bus interface ? on-chip 32-bit sdram controller ? 4-chip select static memory controller multi-level priority, individually maskable, vectored interrupt controller three 16-bit timer/counters two uarts with modem control lines serial peripheral interface (spi) two pio controllers, managing up to 48 general-purpose i/o pins available in a 256-ball bga package power supplies ? vddio 3.3v nominal ? vddcore and vddosc 1.8v nominal -40c to + 85c operating temperature range description the at91c140 is a member of the atmel at91 16- and 32-bit microcontroller family based on the arm7tdmi processor core. this processor has a high performance 32-bit risc architecture with a high density 16-bit instruction set and very low power consumption. in addition, the at91c140 integrates a double ethernet 10/100 base-t mac capable of operating as an ethernet bridge, thus making it ideally suited for networking appli- cations. it supports a wide range of memory devices such as sdram, sram and flash and embeds an extensive array of peripherals. the device is manufactured using atmel?s high-density cmos technology. by combin- ing the arm7tdmi processor core with an expansive assortment of peripheral functions and low-power oscillators and pll on a monolithic chip, the atmel at91c140 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many networking applications. at91 ? arm ? thumb microcontrollers at91c140
2 at91c140 6069a?atarm?05/04 block diagram figure 1. at91c140 block diagram spi peripheral data controller arm7tdmi processor external bus interface sdramc system controller boot rom ethernet 10/100 mbps mac interface ice ethernet 10/100 mbps mac interface 16k bytes sram asb/asb bridge smc jtag debug interface mii phy interface mii phy interface osc. pll interrupt and fast interrupt advanced interrupt controller i/o lines pio controller a i/o lines pio controller b serial peripherals boot dataflash usart a serial port usart b serial port pwm signals timer/counter 0 pwm signals timer/counter 1 pwm signals timer/counter 2 16- or 32-bit data memory bus peripheral bridge
3 at91c140 6069a?atarm?05/04 pinout 256-ball bga package pinout table 1. pinout for 256-ball bga package pin signal name pin signal name pin signal name pin signal name a1 gnd b18 tdi d15 vddio h20 nsoe a2 pb9 b19 nc (1) d16 pa 2 4 j1 ma_txen a3 pb4 b20 nc (1) d17 gnd j2 ma_txd3 a4 pb1 c1 pb10 d18 pa 2 9 j3 ma_txd2 a5 ndsrb c2 pa 2 8 d19 vddcore j4 ma_txd1 a6 nrstb c3 dbw32 d20 irq1 j17 nwr a7 rxdb c4 pb6 e1 nc (1) j18 nwe3 a8 ndsra c5 pb2 e2 gnd j19 nc (1) a9 txda c6 nrib e3 gnd j20 nwe2 a10 pa 2 c7 nctsb e4 pa 2 5 k1 ma_rxd0 a11 pa 3 c8 nria e17 pa 3 0 k2 ma_txclk a12 pa 6 c9 nctsa e18 tst k3 nc (1) a13 pa 1 0 c10 pa 0 e19 irq0 k4 vddio a14 pa 1 3 c11 pa 4 e20 nc (1) k17 nwe1 a15 pa 1 5 c12 pa 8 f1 pb13 k18 nwe0 a16 pa 1 9 c13 pa 1 2 f2 pb12 k19 nce3 a17 nc (1) c14 pa 1 4 f3 gnd k20 nce2 a18 pa 2 3 c15 pa 1 8 f4 vddio l1 ma_rxd1 a19 tdo c16 pa 2 1 f17 vddio l2 ma_rxd2 a20 nc (1) c17 tck f18 fiq l3 ma_rxd3 b1 vddio c18 nc (1) f19 nc (1) l4 ma_rxer b2 pb8 c19 nc (1) f20 spck l17 vddio b3 pb7 c20 pa 3 1 g1 ma_col l18 nce0 b4 pb3 d1 pb11 g2 pb15 l19 nc (1) b5 pb0 d2 pa 2 7 g3 pb14 l20 nce1 b6 ndtrb d3 pa 2 6 g4 ntrst m1 ma_rxclk b7 txdb d4 gnd g17 nrst m2 vddcore b8 ndcda d5 pb5 g18 pa 2 2 m3 ma_rxdv b9 nrsta d6 vddio g19 mosi m4 ma_mdc b10 pa 1 d7 ndcdb g20 miso m17 pllrc b11 pa 5 d8 gnd h1 ma_txd0 m18 nc (1) b12 pa 7 d9 ndtra h2 ma_txer m19 xtalout b13 pa 1 1 d10 rxda h3 ma_crs m20 xtalin b14 vddcore d11 vddio h4 gnd n1 ma_mdio b15 pa 1 6 d12 pa 9 h17 gnd n2 ma_link
4 at91c140 6069a?atarm?05/04 note: 1. nc balls should be left unconnected. b16 pa 2 0 d13 gnd h18 vddio n3 mb_col b17 tms d14 pa 1 7 h19 vddcore n4 gnd n17 gnd t20 sdcs v7 a11 w14 d12 n18 dqm3 u1 mb_rxd0 v8 a14 w15 vddcore n19 vddcore u2 mb_rxd2 v9 a18 w16 d17 n20 vddosc u3 mb_rxclk v10 a22 w17 d20 p1 mb_crs u4 gnd v11 d2 w18 d24 p2 vddcore u5 a1 v12 d6 w19 vddio p3 mb_txd0 u6 vddio v13 d10 w20 nc (1) p4 mb_txd3 u7 a8 v14 d14 y1 nc (1) p17 ras u8 gnd v15 nc (1) y2 mb_mdio p18 dqm0 u9 a17 v16 d19 y3 a2 p19 dqm1 u10 vddio v17 d23 y4 a3 p20 dqm2 u11 d3 v18 d26 y5 a6 r1 mb_txer u12 d7 v19 nc (1) y6 a10 r2 mb_txd1 u13 gnd v20 d29 y7 a13 r3 mb_txen u14 d16 w1 mb_mdc y8 a16 r4 vddio u15 vddio w2 nc (1) y9 a20/ba1 r17 vddio u16 d22 w3 nc (1) y10 a23 r18 sda10 u17 gnd w4 mb_link y11 d0 r19 cas u18 d27 w5 a5 y12 d4 r20 we u19 nc (1) w6 a9 y13 d8 t1 mb_txd2 u20 d30 w7 a12 y14 d11 t2 mb_txclk v1 mb_rxd3 w8 a15 y15 d13 t3 mb_rxd1 v2 mb_rxdv w9 a19/ba0 y16 d15 t4 mb_rxer v3 nc (1) w10 a21 y17 d18 t17 d28 v4 a0 w11 d1 y18 d21 t18 d31 v5 a4 w12 d5 y19 d25 t19 sdck v6 a7 w13 d9 y20 nc (1) table 1. pinout for 256-ball bga package (continued) pin signal name pin signal name pin signal name pin signal name
5 at91c140 6069a?atarm?05/04 mechanical overview of the 256-ball bga package figure 2 below shows the orientation of the 256-ball bga package. for a detailed mechanical description, see ?mechanical characteristics and packaging? on page 162. figure 2. 256-ball bga package orientation (top view) a b c d e f g h j k l m n p r t u v w y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
6 at91c140 6069a?atarm?05/04 peripheral multiplexing on pio lines the at91c140 features two pio controllers, pioa and piob, multiplexing i/o lines of the peripheral set. the pio controller a manages 32 i/o lines, pa0 to pa31. the pio controller b manages only 16 i/o lines, pb0 to pb15. each i/o line of a pio controller can be multiplexed with a peripheral i/o. multiplexing of the pio controller a is given in table 2 on page 7. multiplexing of the pio controller b is given in table 3 on page 8.
7 at91c140 6069a?atarm?05/04 pio controller a multiplexing table 2. multiplexing on pio controller a i/o line peripheral name signal name description type pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 pa 8 t c l k 0 timer counter clock input 0 input pa 9 t i oa 0 timer counter i/o line a 0 i/o pa 1 0 t i o b 0 timer counter i/o line b 0 i/o pa 1 1 s c k a uart a serial clock i/o pa12 npcs1 serial peripehral chip select 1 output pa 1 3 pa14 npcs2 serial peripheral chip select 2 output pa15 npcs3 serial peripheral chip select 3 output pa 1 6 t c l k 2 timer counter clock 2 input pa 1 7 t i oa 2 timer counter i/o line a 2 i/o pa 1 8 t i o b 2 timer counter i/o line b 2 i/o pa19 aclko arm system clock output pa 2 0 pa 2 1 pa22 npcs0 serial peripheral chip select 0 i/o pa 2 3 pa 2 4 pa 2 5 pa 2 6 pa 2 7 pa 2 8 pa 2 9 pa 3 0 pa 3 1
8 at91c140 6069a?atarm?05/04 pio controller b multiplexing table 3. multiplexing on pio controller b i/o line peripheral name signal name description type pb0 tclk1 timer counter clock input 1 input pb1 tioa1 timer counter i/o line a 1 i/o pb2 tiob1 timer counter i/o line b 1 i/o pb3 pb4 pb5 nria uart a ring indicator input pb6 pb7 pb8 pb9 pb10 pb11 pb12 pb13 pb14 pb15
9 at91c140 6069a?atarm?05/04 signal description table 4. signal description block signal name function type power supplies vddio i/o lines power supply vddcore device core power supply vddosc pll and oscillator power supply gnd ground external bus interface a0-a23 address bus output d0-d31 data bus input/output synchronous dynamic memory controller sdck sdram clock output dqm0-dqm3 sdram byte masks output sdcs sdram chip select output sda10 sdram address line 10 output ras row address strobes output cas column address strobes output we write enable output ba0-ba1 bank address line output static memory controller nce0-nce3 chip selects output nwe0-nwe3 byte select/write enable output nsoe output enable output nwr memory block write enable output pio controller a pa0-pa31 pio controller a i/o lines input/output pio controller b pb0-pb15 pio controller b i/o lines input/output timer counter tclk0-tclk2 timer counter clock 0 to 2 input tioa0-tioa2 timer counter i/o line a 0 to 2 input/output tiob0-tioa2 timer counter i/o line b 0 to 2 input/output serial peripheral interface miso master in/slave out input/output mosi master out/slave in input/output spck serial clock input/output npcs0/nss peripheral chip select 0/slave select input/output npcs1-npcs3 peripheral chip select 1 to 3 output
10 at91c140 6069a?atarm?05/04 uart a and uart b rxda-rxdb receive data input txda-txdb transmit data output nrtsa-nrstb ready to send output nctsa-nctsb clear to send input ndtra-ndtrb data terminal ready output ndsra-ndsrb data set ready input ndcda-ndcdb data carrier detect input nria-nrib ring indicator input mac a interface ma_col mac a collision detect input ma_crs mac a carrier sense input ma_txer mac a transmit error output ma_txd0-ma_txd3 mac a transmit data bus output ma_txen mac a transmit enable output ma_txclk mac a transmit clock input ma_rxd0-ma_rxd3 mac a receive data bus input ma_rxer mac a receive error input ma_rxclk mac a receive clock input ma_rxdv mac a receive data valid output ma_mdc mac a management data clock output ma_mdio mac a management data bus input/output ma_link mac a link interrupt input mac b interface mb_col mac b collision detect input mb_crs mac b carrier sense input mb_txer mac b transmit error output mb_txd0-mb_txd3 mac b transmit data bus output mb_txen mac b transmit enable output mb_txclk mac b transmit clock input mb_rxd0-mb_rxd3 mac b receive data bus input mb_rxer mac b receive error input mb_rxclk mac b receive clock input mb_rxdv mac b receive data valid output mb_mdc mac b management data clock output mb_mdio mac b management data bus input/output mb_link mac b link interrupt input table 4. signal description (continued) block signal name function type
11 at91c140 6069a?atarm?05/04 in-circuit emulator ntrst test reset input tck test clock input tms test mode select input tdi test data input input tdo test data output output miscellaneous nrst reset input fiq fast interrupt input irq0-irq1 interrupt lines input pllrc pll rc filter analog xtalin crystal input analog xtalout external crystal analog tst test mode input dbw32 external data bus width for cs0 (1 = 32 bits) input aclko arm clock output output table 4. signal description (continued) block signal name function type
12 at91c140 6069a?atarm?05/04 arm7tdmi core the arm7tdmi is a three-stage pipeline, 32-bit risc processor. the processor archi- tecture is von neumann load/store architecture, characterized by a single data and address bus for instructions and data. the cpu has two instruction sets: the arm and the thumb instruction set. the arm instruction set has 32-bit wide instructions and pro- vides maximum performance. thumb instructions are 16-bit wide and give maximum code density. instructions operate on 8-bit, 16-bit and 32-bit data types. the cpu has seven operating modes. each operating mode has dedicated banked reg- isters for fast exception handling. the processor has a total of 37 32-bit registers, including six status registers. power supplies the at91c140 has three types of power supply pins: vddcore pins power the core, including the arm7tdmi processor, the memories and the peripherals; voltage is between 1.65v and 1.95v, 1.8v nominal. vddio pins power the i/o lines, including those of the external bus interface and those of the peripherals; voltage is between 3v and 3.6v, 3.3v nominal. vddosc pins power the pll and oscillator cells; voltage is between 1.65v and 1.95v, 1.8v nominal. ground pins are common to all power supplies. system controller the at91c140 features a system controller that takes care of and controls: the test mode the reset the system clocks the chip identifier the system controller manages the reset of all the system and integrates a clock gen- erator, made up of an oscillator and a pll. test the at91c140 features a test pin (tst). this pin must be tied low for normal opera- tions. using the at91c140 with the tst pin at a high level might lead to unpredictable results. reset controller nrst pin the at91c140 is reset by asserting the nrst pin low. it should be asserted for a time adequate to ensure the startup of the osc illator on a power on, and at least 1 aclk cycle for a warm reset. as the aclk switches on the 31,25khz (assuming the crystal is at 16 mhz) as soon as the reset is asserted, it must remain low for at least 32 s. the first instruction fetch happens 10 aclk cycles after the reset releases. system reset a reset initializes the user interface register s to their default states as defined in the peripheral sections of this datasheet and fo rces the arm7tdmi to perform the next instruction fetch from address zero. except for the program counter and the current pro- gram status register, the arm processor registers do not have defined reset states. when nrst is active, the inputs of the at91c140 must be held at valid logic levels to reduce the power consumption to a minimum.
13 at91c140 6069a?atarm?05/04 boot memory and remap command when nrst is released, the pa0 pin is sampled to determine if the arm processor should boot from internal rom or from external memory connected to nce0. the details of the boot operations are described in ?memory controller (mc)? on page 17. the boot program is described in ?boot program? on page 24. after a reset, the rm bit in the mode register reflects the state of the pa0 pin. then, writing this bit at 1 removes the rom from the address 0. writing it at 0 remaps the rom at address 0x0. clock generator the at91c140 features a clock generator based on a 16 mhz oscillator and a pll. it provides all the clocks of the system, including a clock signal named aclk, to the arm processor, to the memory controller and to the external bus interface and to all the embedded peripherals the aclk signal is also provided on the aclko pin, through pio controller a. figure 3 below shows the architecture of the clock generator. figure 3. clock generator after the reset, the aclk clock is running at 31.25 khz. the user can program the lpcs field to speed the boot sequence. the aclkst (arm clock status) bit reflects the clock being used for the arm. when read at 0, aclk is 40 mhz if sa is 0 and 34.3 mhz if sa is 1. when read at 1, aclk is at a frequency according to the value programmed in the lpcs field in the system mode register (sys_mr). chip id the system controller features a chip id register that reads a value of 0x00010221 xtalout 1 6 mhz c rystal xtalin 16mhz oscillator pll x15 aclk 240 mhz div6 lp div lpcs 0 1 pllrc lp sa 0 1 div7 aclko counter and control logic rdy
14 at91c140 6069a?atarm?05/04 system controller user interface base address: 0xff00 0000. table 5. system controller register mapping offset register name register description access reset value 0x0 sys_md system mode register read/write 0x0000 034x 0x4 sys_id system id register read-only 0x0001 0221 0x8 reserved 0xc sys_clkf system clock status register read-only 0x0000001
15 at91c140 6069a?atarm?05/04 system mode register register name: sys_md access: read/write rm: remap 0 =the rom is mapped only at its normal address. 1 =the rom is mapped at its address and at address 0x0. lp: low power mode 0 =the pll is enabled and aclk is the output of the pll divided by 6 or 7. 1 =the pll is disabled and aclk is defined by lpcs. sa: slow arm 0 =the arm divider is 6. 1 =the arm divider is 7. lpcs: low power clock select 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?0?0?? lpcs 76543210 salp??0?0rm lpcs divisor aclk 0 0 2 8 mhz 0 1 16 1 mhz 1 0 64 250 khz 1 1 512 31,25 khz
16 at91c140 6069a?atarm?05/04 system id register register name: sys_id access: read-only system clock status register register name: sys_clkf access: read-only aclkst: arm clock status 0 = arm clock currently using the 240 mhz source (pll). 1 = arm clock currently using the 16 mhz source (oscillator). 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000001 15 14 13 12 11 10 9 8 00000010 76543210 00100001 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????aclkst
17 at91c140 6069a?atarm?05/04 memory controller (mc) architecture the at91c140 architecture is made up of two advanced system buses, the arm asb and the mac asb. both handle a single memory space. the arm asb handles the access requests of the arm7tdmi and the pdc. it also handles the access requests coming from the mac asb. it connects with the external bus interface, the peripheral bridge and the internal memories. it also connects with the mac asb. the mac asb handles the access requests of the dmas of both ethernet macs. it also handles the access requests coming from the the arm asb. it connects essentially with the frame buffer, but also connects with the arm asb. the major advantage of this double-asb architecture is that the ethernet traffic does not occupy the main asb bandwidth, ensuring that the arm7tdmi can perform at its maxi- mum speed while the ethernet traffic goes through the frame buffer. the at91c140 architecture is shown in figure 4. figure 4. at91c140 memory controller architecture arm7tdmi processor main bus arbiter peripheral data controller memory controller arm asb internal rom from master to slave mac asb apb external bus interface maca dma macb dma pa 0 secondary bus arbiter asb-asb bridge peripheral bridge sram frame buffer
18 at91c140 6069a?atarm?05/04 memory map the at91c140 memory map is divided into regions of 256 megabytes. the top memory region (0xf000_0000) is reserved and subdivided for the internal memories and shared memory and the embedded peripherals. the device can define up to five other active external memory regions by means of the static memory controller and sdram memory controller. the memory map is divided between both asbs, as shown in figure 4. all regions except the 16 megabytes between 0xfc00 0000 and 0xfcff ffff are located on the main asb. accesses to locations between 0xfc00 0000 and 0xfcff ffff are routed to the mac asb. the memory map assumes default values on reset. external memory regions can be reprogrammed to other base addresses in the static memory controller or in the sdram controller. note that the internal memory regions have fixed locations that can- not be reprogrammed. there are no hardware locks to prevent incorrect programming of the regions. program- ming two or more regions to have the sa me base address or overlapping two memory regions results in undefined behavior. the arm processor reset vector at address 0x00000000 is mapped into the internal rom or external memory connected on nce0. this selection depends on the pa0 sig- nal pin. after booting, the rom region can be disabled and any external memory can be mapped to the bottom of the memory map by programming smc_csrx or sdramc_addr. figure 5. at91c140 memory map 0x0000 0000 0x0fff ffff 0x1000 0000 0x1fff ffff 0x2000 0000 0x2fff ffff 0x3000 0000 0x3fff ffff 0x4000 0000 0x4fff ffff 0x5000 0000 0xefff ffff 0xf000 0000 0xffff ffff 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 10 x 256m bytes external static memory connected on nce0 unused internal memories and peripherals external static memory connected on nce1 external static memory connected on nce2 external static memory connected on nce3 smc external dynamic memory connected on sdcs sdramc
19 at91c140 6069a?atarm?05/04 figure 6 below shows the mapping of the internal memories and the address space reserved for the peripheral bridge. figure 6. internal memory mapping arm asb arbitration the arm asb is arbitrated with the following priorities: the pdc has the highest priority. the bridge from the mac asb has the middle priority. the arm processor has the lowest priority. mac asb arbitration the mac asb is arbitrated with the following priorities: the bridge from the arm asb has the highest priority. the mac a has the middle priority. the mac b has the lowest priority. asb-asb bridge arbitration the mac asb has two priority levels; the two macs share low priority access and the asb-asb bridge has high priority. the macs do not burst more than four words per access and release the bus request between accesses so the macs share a priority level with a simple round-robin arbitration scheme. the arm is likely to be the only master accessing the mac bus via the bridge and should not perform more than a couple of cycles before releasing the mac bus. care should be taken to prevent other masters on the arm bus holding the mac bus for more than a few cycles. otherwise, the macs drop frames due to fifo overflow or underflow. when a master on one bus accesses a slave on the other bus, the following operations occur: the local bus arbiter arbitrates the master?s request for the local asb bus if it does not already have access to the bus. when the local bus arbiter grants the local bus to the master, the master initiates a cycle with an address corresponding to a slave on the remote bus. the bridge is selected as the slave on the local bus and responds by inserting wait cycles. the bridge also requests the remote bus from the remote bus arbiter. 0xf8ff ffff 0xfa00 0000 0xfaff ffff 0xfb00 0000 0xfbff ffff 0xfc00 0000 0xfcff ffff 0xfd00 0000 0xfdff ffff 0xfd00 0000 0xfeff ffff 0xff00 0000 0xffff ffff 144m bytes 16m bytes 16m bytes 16m bytes 16m bytes 16m bytes reserved reserved peripherals reserved reserved reserved frame buffer 0xf900 0000 0xf9ff ffff rom actual siz e 1k byte 0xff00 0000 16m bytes 16m bytes 16k byte s
20 at91c140 6069a?atarm?05/04 when the bridge is granted the remote bus, the two asb buses are coupled and the transfer completes. the asb performs pipelined arbitration. the asb-asb bridge can only request the bus when the address of the slave is available. for this reason, the asb-asb bridge inserts a wait cycle during the arbitration cycle on the remote bus because it cannot request the bus early. boot mode the at91c140 has an integrated 1-kbyte rom to support the boot software. when the device is released from reset, the pin pa0 is sampled by the memory controller. if sam- pled low, the internal rom becomes accessible from the address 0x0, so that the arm processor starts execution of the boot program. note that the rom remains accessible at its normal address. if the pin pa0 is sampled high at reset, the mapping does not change and the external memory connect ed on nce0 should contain a valid boot sequence. the level of the pin pa0 at resets is indicated by the rm flag in the system mode regis- ter (sys_md). then, the rm bit can be written at any value to map to or remove the rom from address 0x0. if pa0 is asserted on reset, the boot program in rom is executed. the boot program is described in ?boot program? on page 24. figure 7 below shows the mapping of the rom depending on the boot mode. figure 7. rom mapping depending on the boot mode endianness the at91c140 memory controller operates in little-endian mode only. the user has to make sure that the data structures used by the arm7tdmi, the ethernet dmas and the pdc are compliant with this mode of byte arrangement. 0x0000 0000 0x0fff ffff 256m bytes rom rm = 0 1k byte external memory connected on nce0 external memory connected on nce0 0x0000 03ff 0x0000 0400 rm = 1
21 at91c140 6069a?atarm?05/04 peripherals the peripheral bridge allows access to the embedded peripheral user interfaces. it is optimized for low power consumption, as it is built without usage of any clock. however, any access on the peripheral is performed in two cycles. the at91c140 peripherals are designed to be programmed with a minimum number of instructions. each peripheral has 16k bytes of address space allocated in the upper part of the address space. peripheral registers all of the peripheral registers are 32-bits wide and support only aligned accesses. when a misaligned access is performed within the peripheral address space, the access is automatically performed at the lower aligned address. all undefined or unused register bits (mar ked ?-?) read 0. it is recommended to write them at 0 for software upward compatibility.
22 at91c140 6069a?atarm?05/04 peripheral memory map figure 8 below gives the mapping of the peripherals integrated in the at91c140. figure 8. peripheral memory map 16k bytes peripheral name size 16k bytes 16k bytes 0 xff00 4000 0xff00 7fff 16k bytes reserved 0 xff00 8000 0xff00 bfff sdramc sdram controller pioa 0 xff00 c000 0xff00 3fff 0xff02 4000 0xff02 ffff 0xff00 ffff tc0, tc1, tc2 0 xff01 4000 0xff01 7fff aic 0 xff03 0000 0xff03 3fff maca ethernet mac a 0 xff03 4000 uart a universal asynchronous receiver transmitter a 0 xff01 8000 0xff01 bfff uart b universal asynchronous receiver transmitter b 0 xff01 c000 0xff01 ffff reserved 0xff03 c000 0xffff efff spi serial peripheral interface 0 xff02 0000 0xff02 3fff 0 xff00 0000 sysc smc system controller 16k bytes static memory controller 16k bytes parallel i/o controller a 16k bytes piob 0 xff01 0000 0xff01 3fff parallel i/o controller b 16k bytes timer counter channel 0, 1 and 2 16k bytes 16k bytes advanced interrupt controller 16k bytes 0xff03 7fff macb ethernet mac b 0 xff03 8000 16k bytes 0xff03 bfff aic 0 xffff f000 0xffff ffff 16k bytes advanced interrupt controller aic is mapped at both addresse s
23 at91c140 6069a?atarm?05/04 peripheral data controller (pdc) pdc overview the at91c140 features a six-channel peripheral data controller (pdc) dedicated to the two on-chip uarts and the spi. one pdc channel is connected to the receiving channel and one to the transmitting channel of each uart and of the spi. each pdc channel operates as dma (direct memory access). the user interface of a pdc channel is integrated in the memory space of each periph- eral. it contains a 32-bit address pointer register and a 16-bit count register. when the programmed number of bytes is transferred, an end-of-transfer signal is sent to the peripheral and is visible in the peripheral status register. this status bit might trigger an interrupt. pdc channel priority the transfer requests from the peripherals are treated in the order they happen. when several transfer requests happen in the same cycle, the following priority order is applied: the uart a receiver the uart a transmitter the uart b receiver the uart b transmitter the spi receiver the spi transmitter
24 at91c140 6069a?atarm?05/04 boot program the at91c140 can boot in several ways as explained below. when the arm7tdmi processor is released from reset it basically attempts a fetch from address 0x00000000. depending on an hardware configuration, the memory mapping can be altered and thus modify how the system boots. boot mode when the master reset is released, the pin pa0 is latched. its state defines how the sys- tem boots. when pa0 is latched at 1, the at91c140 is said to be configured in external boot mode. the initial state of the ebi maps the 1-mbyte address range starting from 0x00000000 in the external device selected by nce0. in this boot mode, nce0 is assumed to be connected to an external memory device containing the suitable boot code. when pa0 is latched at 0, the at91c140 is said to be configured in internal boot mode. the internal boot rom normally located at base address 0xf9000000 is aliased at address 0x00000000. in this boot mode, the arm processor executes the first instruc- tions out of the internal boot rom. the boot mode is reflected by the rm bit in register sys_md. reading rm at 0 indi- cates that the boot rom is aliased at base address 0x00000000, eventually overlapping the memory layout defined by the smc and the sdramc registers. reading rm at 1 indicates that the boot rom can be accessed only from base address 0xf9000000. writ- ing rm allows to select the mapping of the boot rom under software control. hardware connection of the dataflash the internal boot software provides the at91c140 with the capability of booting from an external serial dataflash connected on the on-chip spi interface as described above. when the internal boot software is used in conjunction with dataflash, the latter must be connected to the at91c140 as shown below in figure 9. figure 9. dataflash connection internal boot software the internal boot code goes through the following steps in sequence: the processor enters the supervisor mode and all the interrupts are masked. a branch is executed into the rom alias based from 0xf9000000. the rom alias based at 0x00000000 is removed by writing the rm bit at 1. the clock is programmed at the highest frequency achievable without using the on- chip pll (i.e. the frequency of the crystal divided by 2). the on-chip spi interface is setup to prepare for communications with dataflash. a bunch of data is downloaded from the dataflash. this data is expected to contain a formatted header describing the contents of the dataflash. this header is analyzed to verify whether a dataflash is actually present and contains valid executable code. at91c140 npcs0/pa22 miso dataflash cs si mosi spck so ck
25 at91c140 6069a?atarm?05/04 if the dataflash is there and contains valid executable code, this code is downloaded into a location specified by the header, and an absolute branch to this code is performed. if the dataflash is missing, or if the header is not valid, an absolute branch to address 0x00000000 is performed. a suitable memory device should be mapped at this address and contain the expected code. dataflash header details to ensure correct operation of the boot out of dataflash, the dataflash must contain a valid header. this header contains several fields which define how the application soft- ware residing further must be handled. the structure of the dataflash header is illustrated below in table 6. note: 1. the field address is respective to the dataflash space. 0x00 corresponds to the first location of the dataflash. the magic field contains a predefined magic number which allows identification of the suitability of the dataflash. the value of this field must be 0x0075c221 to allow the boot routine to proceed. if another value is read, the boot code gives up the download and branches to 0x0000 0000 where the real application code is expected. the dsrc field contains the address where the code to be downloaded resides in dataflash. this address is respective to the dataflash address space ( not the arm processor address space) and follows the non-linear addressing scheme defined in the documentation of the dataflash. note that all bits are not necessarily significant, depending on the specific dataflash device. the ddst field contains the destination address where the downloaded code will be copied. this address is respective to the arm processor address space. typically, this address should point into some internal ram. the dsize field contains the number of bytes to be downloaded. this value is exclusive of the header. it must be even. the entry field contains the address where the boot routine must branch when the download is complete. it is the entry point of the newly downloaded software. although this is not required, the entry field equals the ddst field in most cases. reserved resources the internal boot code needs some resources to operate correctly, especially as it pro- grams some on-chip peripherals. these must not be assumed to be in their reset state when the control is given to the application code. the concerned peripherals are: the clock management system the spi interface the pio pin pa22 the rm bit table 6. header structure field address field name field length 0x00 (1) magic 4 bytes 0x04 dsrc 4 bytes 0x08 ddst 4 bytes 0x0c dsize 4 bytes 0x10 entry 4 bytes
26 at91c140 6069a?atarm?05/04 the internal boot code also uses some internal ram locations to store temporary data. these reside in the first 64 bytes of ram, i.e. from 0xfd00 ffc0 to 0xfd00 ffff. the ddst, dsize fields of the dataflash header must not define a memory area overlap- ping the locations used by the internal boot routine. the entry field must not point into this area.
27 at91c140 6069a?atarm?05/04 external bus interface (ebi) the external bus interface (ebi) generates the signals that control access to external memories or peripheral devices. it contains two controllers, the sdram controller and the static memory controller and manages the sharing of data and address busses between both of these controllers. signal multiplexing table 7. signal description and multiplexing name description controlled by smc controlled by sdramc [d31:0] data bus [d31:0] [d31:0] [a9:0] address lines 0 to 9 [a9:0] [a9:0] a10 address line 10 a10 sda10 sdram controller address line 10 a10 [a12:11] address lines 11 to 12 [a12:11] [a12:11] [a18:13] address lines 13 to 18 [a18:13] a19/ba0 address line 19 or bank address 0 a19 ba0 a20/ba1 address line 20 or bank address 1 a20 ba1 [a23:21] address lines 21 to 23 [a23:21] sdck sdram clock sdck sdcs sdram controller chip select sdcs ras sdram row signal ras cas sdram column signal cas we sdram write enable we dqm0-dqm3 sdram data mask enable signals dqm0-dqm3 nce0-nce3 active low chip enable nce0-nce3 nwe0-nwe3 active low byte select/write strobe signals nwe0-nwe3 nwr active low write strobe signals nwr nsoe active low read enable signal nsoe
28 at91c140 6069a?atarm?05/04 sdram controller (sdramc) description the sdram controller (sdramc) extends the memory capabilities of a chip by provid- ing the interface to an external 16-bit or 32-bit sdram device. the page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. it supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. the maximum addressable sdram size is 256m bytes. the sdram controller supports a read or write burst length of one location. it keeps track of the active row in each bank, thus maximizing sdram performance, e.g., the application may be placed in one bank and data in the other banks. so as to optimize performance, it is advisable to avoid accessing different rows in the same bank. block diagram figure 10. sdram controller block diagram memory controller apb sdck sdcs a[12:11, 9:0] sdramc ba[1:0] ras cas we dqm[3:0] user interface system controller aclk d[31:0] sdramc chip select sda10
29 at91c140 6069a?atarm?05/04 i/o lines description application example hardware interface figure 11 below shows an example of an sdram device connection to the sdram controller by using a 32-bit data bus width. figure 12 shows an example of an sdram device connection by using a 16-bit data bus width. figure 11. sdram controller connections to sdram devices: 32-bit data bus width table 8. i/o line description name description type active level sdck sdram clock output sdcs sdram controller chip select output low ba[1:0] bank select signals output high ras row signal output low cas column signal output low we sdram write enable output low dqm[3:0] data mask enable signals output low a [12:11] sda10 a[9:0] address bus output d[31:0] data bus i/o sdram controller d0-d31 a0-a9, sda10, a11 ras cas sdck we dqm0 2m x 8 sdram d0-d7 a0-a11 ras cas clk cke cke we dqm cs ba0 ba1 dqm1 dqm2 dqm3 sdcs d0-d7 d8-d15 a19/ba0 a20/ba1 a0-a11 ba0 ba1 2m x 8 sdram d0-d7 ras cas clk we dqm cs ba0 ba1 ba0 ba1 2m x 8 sdram d0-d7 ras cas clk we dqm cs ba0 ba1 d16-d23 d24-d31 ba0 ba1 2m x 8 sdram d0-d7 ras cas clk we dqm cs ba0 ba1 ba0 ba1 dqm0 dqm1 dqm3 dqm2 we we we we a0-a11 vdd vdd cke vdd cke vdd a0-a11 a0-a11 a0-a11 a0-a11 a0-a11 a0-a11
30 at91c140 6069a?atarm?05/04 figure 12. sdram controller connections to sdram devices: 16-bit data bus width software interface the sdram controller?s function is to make the sdram device access protocol trans- parent to the user. t able 9 to table 13 illustrate the sdram device memory mapping therefore seen by the user in correlation with the device structure. various configura- tions are illustrated. 32-bit memory data bus width 16-bit memory data bus width sdram controller d0-d31 a0-a9, sda10, a11 ras cas sdck we dqm0 2m x 8 sdram d0-d7 a0--a11 ras cas clk we dqm cs ba0 ba1 dqm1 sdcs d0-d7 d8-d15 a19/ba0 a20/ba1 a0-a11 ba0 ba1 2m x 8 sdram d0-d7 a0-a11 ras cas clk we dqm cs ba0 ba1 a0- a11 ba0 ba1 dqm0 dqm1 sdwe sdwe vdd cke vdd cke a0-a11 table 9. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m[1:0] bk[1:0] row[10:0] column[8:0] m[1:0] table 10. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 2726252423222120191817161514131211109876543210 bk[1:0] row[11:0] column[7:0] m[1:0] table 11. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m0 bk[1:0] row[10:0] column[8:0] m0 bk[1:0] row[10:0] column[9:0] m0
31 at91c140 6069a?atarm?05/04 sdram device initialization the initialization sequence is generated by software. the sdram devices are initialized by the following sequence: 1. a minimum pause of 200 s is provided to precede any signal toggle. 2. an all banks precharge command is issued to the sdram devices. 3. eight auto-refresh (cbr) cycles are provided. 4. a mode register set (mrs) cycle is issued to program the parameters of the sdram devices, in particular cas latency and burst length. 5. a normal mode command is provided, 3 clocks after t mrd is met. 6. perform a dummy access in the sdram memory space to initialize the state machine. 7. write refresh rate into the count field in the sdramc refresh timer register. (refresh rate = delay between refresh cycles). after these six steps, the sdram devices are fully functional. the commands (nop, mrs, cbr, normal mode) are generated by programming the command field in the sdramc mode register. table 12. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 2726252423222120191817161514131211109876543210 bk[1:0] row[11:0] column[7:0] m0 bk[1:0] row[11:0] column[8:0] m0 table 13. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 2726252423222120191817161514131211109876543210 bk[1:0] row[12:0] column[7:0] m0
32 at91c140 6069a?atarm?05/04 figure 13. sdram device initialization sequence t rp t rc t mrd sdck a[9:0] sda10 a [12:11] sdcs ras cas we nbs inputs stable for 200 sec precharge all banks 1st auto-refresh 8th auto-refresh mrs command valid command
33 at91c140 6069a?atarm?05/04 sdram controller write cycle the sdram controller allows burst access or single access. to initiate a burst access, the sdram controller uses the transfer type signal provided by the master requesting the access. if the next access is a sequential write access, writing to the sdram device is carried out. if the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the sdram controller generates a precharge command, activates the new row and initiates a write command. to comply with sdram timing parameters, additional clock cycles are inserted between precharge/active (t rp ) commands and active/write (t rcd ) commands. for a definition of these timing parameters, refer to the ?sdramc configuration register? on page 39. this is described in figure 14 below. figure 14. write burst, 32-bit sdram access sdck sdcs ras cas a [12:0] d [31:0] t rcd = 3 dna we dnb dnc dnd dne dnf dng dnh dni dnj dnk dnl row n col a col b col c col d col e col f col g col h col i col j col k col l
34 at91c140 6069a?atarm?05/04 sdram controller read cycle the sdram controller allows burst access or single access. to initiate a burst access, the sdram controller uses the transfer type signal provided by the master requesting the access. if the next access is a sequential read access, reading to the sdram device is carried out. if the next access is a sequential read access, but the current access is to a boundary page, or if the next access is in another row, then the sdram controller generates a precharge command, activates the new row and initiates a read command. to comply with sdram timing parameters, an additional clock cycle is inserted between the precharge/active (t rp ) command and the active/read (t rcd ) com- mand, after a read command, additional wait states are generated to comply with cas latency. the sdram controller supports a cas latency of two. for definition of these timing parameters, refer to ?sdramc configuration register? on page 39. this is described in figure 15 below. figure 15. read burst, 32-bit sdram access sdck sdcs ras cas a[12:0] d[31:0] (input) dna we dnb dnc dnd dne dnf row n col a col b col c col d col e col f t rcd = 3 cas = 2
35 at91c140 6069a?atarm?05/04 border management when the memory row boundary has been reached, an automatic page break is inserted. in this case, the sdram controller generates a precharge command, activates the new row and initiates a read or write command. to comply with sdram timing parameters, an additional clock cycle is inserted between the precharge/active (t rp ) command and the active/read (t rcd ) command. this is described in figure 16 below. figure 16. read burst with boundary row access sdck sdcs ras cas a [12:0] d [31:0] t rp = 3 we row m col a col a col b col c col d col e dna dnb dnc dnd t rcd = 3 cas = 3 col b col c col d dma dmb dmc dmd row n dme
36 at91c140 6069a?atarm?05/04 sdram controller refresh cycles an auto-refresh command is used to refresh the sdram device. refresh addresses are generated internally by the sdram device and incremented after each auto-refresh automatically. the sdram controller generates these auto-refresh commands periodi- cally. a timer is loaded with the value in the register sdramc_tr that indicates the number of clock cycles between refresh cycles. when the sdram controller initiates a refresh of the sdram device, internal memory accesses are not delayed. however, if the arm tries to access the sdram, it is held until the refresh cycle has completed. see figure 17 below. figure 17. refresh cycle followed by a read access sdck sdcs ras cas a [12:0] d [31:0] (input) we dnb dnc dnd col c col d cas = 2 row m col a row n dma t rp = 3 t rc = 8 t rcd = 3
37 at91c140 6069a?atarm?05/04 sdram user interface base address: 0xff00 8000 sdramc mode register register name: sdramc_mr access type: read/write reset value: 0x00000010 mode: sdramc command mode this field defines the command issued by the sdram controller when the sdram device is accessed. table 14. sdram controller register mapping offset register name register description access reset state 0x00 sdramc_mr sdramc mode register read/write 0x00000000 0x04 sdramc_tr sdramc refresh timer register read/write 0x00000800 0x08 sdramc_cr sdramc configuration register read/write 0x0299c140 0x0c sdram_16bit sdram 16-bit configuration read/write 0x00000001 0x10 sdramc_addr base address for sdcs read/write 0x00000040 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????mode 76543210 mode ?????? mode description 0 0 0 normal mode. any access to the sdram is decoded normally. 0 0 1 the sdram controller issues a nop command when the sdram device is accessed regardless of the cycle. 0 1 0 the sdram controller issues an ?all banks precharge? command when the sdram device is accessed regardless of the cycle. 0 1 1 the sdram controller issues a ?load mode register? command when the sdram device is accessed regardless of the cycle. the address offset with respect to the sdram device base address is used to program the mode register. for instance, when this mode is activated, an access to the ?sdram_base + offset? address generates a ?load mode register? command with the value ?offset? written to the sdram device mode register. 1 0 0 the sdram controller issues a ?refresh? command when the sdram device is accessed regardless of the cycle. prior to this, an ?all banks precharge? command must be issued. others reserved
38 at91c140 6069a?atarm?05/04 sdramc refresh timer register register name: sdramc_tr access type: read/write reset value: 0x00000800 count: sdramc refresh timer count this 12-bit field is loaded into a timer that generates the refresh pulse. each time the refresh pulse is generated, a refresh burst is initiated. the value to be loaded depends on the sdramc clock frequency (mck: master clock), the refresh rate of the sdram device and the refresh burst length where 15.6 s per row is a typical value for a burst of one length. to refresh the sdram device even if the reset value is not equal to 0, this 12-bit field must be written. if this condition is not satisfied, no refresh command is issued and no refresh of the sdram device is carried out. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? count 76543210 count
39 at91c140 6069a?atarm?05/04 sdramc configuration register register name: sdramc_cr access type: read/write reset value: 0x0299c140 nc: number of column bits reset value is 8 column bits. nr: number of row bits reset value is 11 row bits. nb: number of banks reset value is two banks. twr: write recovery delay reset value is two cycles. this field defines the write recovery time in number of cycles. number of cycles is between 2 and 15. if twr is less than or equal to 2, two clock periods are inserted by default. 31 30 29 28 27 26 25 24 ????? tras 23 22 21 20 19 18 17 16 tras trcd trp 15 14 13 12 11 10 9 8 trp trc twr 76543210 twr 1 0 nb nr nc nc column bits 008 019 1010 1111 nr row bits 00 11 01 12 10 13 11 reserved nb number of banks 02 14
40 at91c140 6069a?atarm?05/04 trc: row cycle delay reset value is eight cycles. this field defines the delay between a refresh and an activate command in number of cycles. number of cycles is between 2 and 15. if trc is less than or equal to 2, two clock periods are inserted by default. trp: row precharge delay reset value is three cycles. this field defines the delay between a precharge command and another command in number of cycles. number of cycles is between 2 and 15. if trp is less than or equal to 2, two clock periods are inserted by default. trcd: row to column delay reset value is three cycles. this field defines the delay between an activate comma nd and a read/write command in number of cycles. number of cycles is between 2 and 15. if trcd is less than or equal to 2, two clock periods are inserted by default. tras: active to precharge delay reset value is five cycles. this field defines the delay between an activate command and a precharge command in number of cycles. number of cycles is between 2 and 15. if tras is less than or equal to 2, two clock periods are inserted by default. sdramc address register register name: sdramc_addr access type: read/write sdcs_addr this field defines the eight most significant bits of the base address of the sdramc. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sdcs_addr
41 at91c140 6069a?atarm?05/04 static memory controller (smc) the at91c140 features a static memory controller (smc), that enables interfacing with a wide range of external static memory on peripheral devices, including flash, rom, static ram, and parallel peripherals. the smc provides a glueless memory interface to external memory using common address, data bus and dedicated control signals. the smc is highly programmable and has up to 24 bits of address bus, a 32- or 16-bit data bus and up to four chip select lines. the smc supports different access protocols allowing single clock-cycle accesses. the smc is programmed as an internal peripheral that has a standard apb bus interface and a set of memory-mapped registers. it shares the external address and data buses with the sdramc and any external bus master. external memory mapping the memory map associates the internal 32-bit address space with the external 24-bit address bus. the memory map is defined by programming the base address and page size of the external memories. note that address bits a2 to a23 are significant for 32-bit memories whereas address bits a1 to a23 are significant for 16-bit memories. if the physical memory-mapped device is smaller than the programmed page size, it wraps around and appears to be repeated within the page. the smc correctly handles any valid access to the memory device within the page. in the event of an access request to an address outside any programmed page, an abort signal is generated by the internal decoder. two types of abort are possible: instruction prefetch abort and data abort. the corresponding exception vector addresses are 0x0000000c and 0x00000010. it is up to the system programmer to program the excep- tion handling routine used in case of an abort. pin description table 15 below lists the pins used by the smc to control external memories. data bus width a data bus width of 32 or 16 bits can be selected for each chip select. this option is con- trolled by the dbw field in the chip sele ct register (smc_csr) of the corresponding chip select. the at91c140 boots up with a data bus as defined by the dbw32 pin. if tied high, chip select 0 is automatically setup to be 32-bit wide. if tied low, the chip select 0 is config- ured to be 16-bit wide. the dbw bit in smc_csr resets accordingly to the level of dbw32. table 15. smc pin description fpdram description type [a23:0] address bus output [d31:0] data bus i/o nce0-nce3 active low chip enable output nwe0-nwe3 active low byte select/write strobe signals output nwr active low write strobe signals output nsoe active low read enable signal output
42 at91c140 6069a?atarm?05/04 byte write or byte select mode each chip select can be individually programmed to operate in byte write or byte select mode. the byte write mode supports four (32-bit bus) or two (16-bit bus) byte writes and a single read signal. the byte select mode selects the appropriate byte(s) using four (32-bit bus) or two (16-bit bus) byte-select lines and separate read and write signals. this option is controlled by the bat bit in the chip select register (smc_csr0 to smc_csr3). the byte write mode is used to connect four 8-bit devices on a 32-bit bus or two 8-bit devices on a 16-bit bus. for a 32-bit bus: the nwe0 signal is used as the write enable signal for byte 0. the nwe1 signal is used as the write enable signal for byte 1. the nwe2 signal is used as the write enable signal for byte 2. the nwe3 signal is used as the write enable signal for byte 3. the nsoe signal enables memory reads to all memory blocks. for a 16-bit bus: the nwe0 signal is used as the write enable signal for byte 0. the nwe1 signal is used as the write enable signal for byte 1. the nsoe signal enables memory reads to all memory blocks. the byte select mode is used to connect one 32-bit device or tw o 16-bit devices on a 32-bit data bus or one 16-bit device on a 16-bit data bus. for a 32-bit bus: the nwe0 signal is used to select byte 0 for read and write operations. the nwe1 signal is used to select byte 1 for read and write operations. the nwe2 signal is used to select byte 2 for read and write operations. the nwe3 signal is used to select byte 3 for read and write operations. the nwr signal is used as the write enable signal for the memory block. the nsoe signal enables memory reads to the memory block. for a 16-bit bus: the nwe0 signal is used to select byte 0 for read and write operations. the nwe1 signal is used to select byte 1 for read and write operations. the nwr signal is used as the write enable signal for the memory block. the nsoe signal enables memory reads to the memory block. read protocols the smc provides two alternative protocols for external memory read access; standard and early read. the difference between the two protocols lies in the timing of the nsoe (read cycle) waveform. the protocol is selected by the drp field in the memory control register (smc_mcr) and is valid for all memory devices. standard read protocol is the default protocol after reset. standard read protocol standard read protocol implements a read cycle in which nsoe and the write strobes are similar. both are active during the second half of the clock cycle. the first half of the clock cycle allows time to ensure completion of the previous access, as well as the out- put of address and nce before the read cycle begins.
43 at91c140 6069a?atarm?05/04 during a standard read protocol external memory access, the chip enable signal snce0 to nce3 are set low and the address lines are valid at the beginning of the access, whereas nsoe goes low only in the second half of the master clock cycle to avoid bus conflict. the write strobes are the same in both protocols. the write strobes always go low in the second half of the master clock cycle. early read protocol early read protocol provides more time for a read access from the memory by asserting nsoe at the beginning of the clock cycle. in the case of successive read cycles in the same memory, nsoe remains active continuously. since a read cycle normally limits the speed of operation of the external memory system, early read protocol allows a faster clock frequency to be used. however, an extra wait state is required in some cases to avoid contention on the external bus. in early read protocol, an early read wait state is automatically inserted when an exter- nal write cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent read cycle begins. this wait state is generated in addition to any other programmed wait states (i.e., data float wait). no wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type or between external and internal memory accesses. write protocol during a write cycle, the data becomes valid after the falling edge of the write strobe sig- nal and remains valid after the rising edge of the write strobe. the external write strobe waveform on the appropriate write strobe pin is used to control the output data timing to guarantee this operation. thus, it is necessary to avoid excessive loading of the write strobe pins, which could delay the write signal too long and cause a contention with a subsequent read cycle in standard protocol. in early read protocol, the data can remain valid longer than in stan- dard read protocol due to the additional wait cycle that follows a write access. wait states the smc can automatically insert wait states. the different types of wait states are: standard wait states data float wait states chip select change wait states early read wait states, as described in ?early read protocol? above. standard wait states each chip select can be programmed to insert one or more wait states during an access on the corresponding device. this is done by setting the wse field in the corresponding smc_csr. the number of cycles to insert is programmed in the nws field in the same register. when no wait state is programmed (wse = 0), the nwe signal lasts only one-half cycle. if at least one wait state is programmed, the nwe signal lasts an integer number of cycles, accordingly to the number of wait states programmed. data float wait states some memory devices are slow to release the external bus. for such devices it is nec- essary to add wait states (data float waits) after a read access before starting a write access or a read access to a different external memory. the data float output time (tdf) for each external memory device is programmed in the tdf field of the smc_csr register for the corresponding chip select. the value (0 - 7 clock cycles) indicates the number of data float waits to be inserted and represents the time allowed for the data output to go to high impedance after the memory is disabled. the smc keeps track of the programmed exte rnal data float time even when it makes internal accesses to ensure that the external memory system is not accessed while it is still busy.
44 at91c140 6069a?atarm?05/04 internal memory accesses and consecutive accesses to the same external memory do not insert added data float wait states. when data float wait states are being used, the smc prevents the sdram controller from accessing the external data bus. chip select change wait states a chip select wait state is automatically inserted when consecutive accesses are made to two different external memories (if no wait states have already been inserted). if any wait states have already been inserted (e.g., data float wait), then none are added. signal waveforms figure 18 on page 45 shows a write to memory 0 followed by a write and a read to mem- ory 1. smc_csr0 is programmed for one wait state with bat = 0 and tdf = 0. smc_csr1 is programmed for zero wait states with bat = 1 and tdf = 0. early read protocol is enabled. the write to memory 0 is a word access and therefore all four nwe strobes are active. as bat = 0, they are configured as write strobes and have the same timing as nwr. as the access employs a single wait state, the write strobe pulse is one clock cycle long. there is a chip select change wait state between the memory 0 write and the memory 1 write. the new address is output at the end of the memory 0 access, but the strobes are delayed for one clock cycle. the write to memory 1 is a half-word access to an odd half-word address and, therefore, nwe2 and nwe3 are active. as bat = 1, they are configured as byte select signals and have the same timing as nce. as the access has no internal wait states, the write strobe pulse is one- half clock cycle long. data and address are driven until the write strobe rising edge is sensed at the at91c140 pin to guarantee positive hold times. there is an early read wait state between memory 1 write and memory 1 read to provide time for the at91c140 to disable the output data before the memory is read. if the read was normal mode, i.e., not early, the nsoe strobe would not fall until the rising edge of aclk and no wait state would be inserted. if the write and early read were to different memories, then the early read wait state is not required as a chip select wait state will be implemented. the read from memory 1 is a byte access to an address with a byte offset of 2 and therefore only nwe2 is active.
45 at91c140 6069a?atarm?05/04 figure 18. write to memory 0, write and read to memory 1 figure 19 on page 46 shows a write and a read to memory 0 followed by a read and a write to memory 1. smc_csr0 is programmed for zero wait states with bat = 0 and dft = 0. smc_csr1 is programmed for zero wait states with bat = 1 and dft = 1. smc_mcr is programmed for normal reads from all memories. the write to memory 0 is a byte access and, therefore, only one nwe strobe is active. as bat = 0, they are configured as write strobes and have the same timing as nwr. the memory 0 read immediately follows the write as early reads are not configured and an early read wait state is not required. as early reads are not configured, the read strobe pulse is one-half clock cycle long. there is a chip select change wait state between the memory 0 write and the memory 1 read. the new address is output at the end of the memory 0 access but the strobes are delayed for one clock cycle. the write to memory 1 is a half-word access to an odd half-word address and, therefore, nwe2 and nwe3 are active. as bat = 1, they are configured as byte select signals and have the same timing as nce. as dft = 1 for memory 1, a wait state is implemented between the read and write to provide time for the memory to stop driving the data bus. dft wait states are only imple- mented at the end of read accesses. aclk nce0 nce1 a nwr nsoe nwe0 nwe1 nwe2 nwe3 d out d in internal wait state chip select wait state early read wait state
46 at91c140 6069a?atarm?05/04 the read from memory 1 is a byte access to an address with a byte offset of 2 and, therefore, only nwe2 is active. figure 19. write and read to memory 0, read and write to memory 1 aclk nce0 nce1 a nwr nsoe nwe0 nwe1 nwe2 nwe3 d out d in chip select wait state data float wait state
47 at91c140 6069a?atarm?05/04 smc user interface the memory control register (smc_mcr) is used to program the number of active chip selects and data read protocol. four chip select registers (smc_csr0 to smc_csr3) are used to program the parameters for the individual external memories. each smc_csr must be programmed with a different base address, even for unused chip selects. the smc_csr register resets according to the dbw32 pin. during the boot sequence, the chip select registers must be programmed as required depending on the devices connected on the external bus. the chip select addresses that are programmed take effect immediately. wait states also take effect immediately when they are programmed to optimize boot program execution. table 16. smc register mapping offset register name register description access reset value 0x00 smc_csr0 chip select register read/write 0x0000203d 0x0000203e 0x04 smc_csr1 chip select register read/write 0x10000000 0x08 smc_csr2 chip select register read/write 0x20000000 0x0c smc_csr3 chip select register read/write 0x30000000 0x10 ? reserved ?? 0x14 ? reserved ?? 0x18 ? reserved ?? 0x1c ? reserved ?? 0x20 ? reserved ?? 0x24 smc_mcr memory control register read/ write 0x0
48 at91c140 6069a?atarm?05/04 smc chip select register register name: smc_csr0..smc_csr3 access: read/write dbw: data bus width nws: number of wait states wse: wait state enable mws: multiply wait states pages: page size 31 30 29 28 27 26 25 24 ba 23 22 21 20 19 18 17 16 ba ???? 15 14 13 12 11 10 9 8 ? ? csen bat tdf pages 76543210 pages mws wse nws dbw dbw data bus width 0 0 reserved 0 1 16-bit external bus 1 0 32-bit external bus 1 1 reserved nws wse wait states number mws = 0 mws = 1 x x x 0 0 0 0 0 0 1 1 8 0 0 1 1 2 16 0 1 0 1 3 24 0 1 1 1 4 32 1 0 0 1 5 40 1 0 1 1 6 48 1 1 0 1 7 56 1 1 1 1 8 64 pag e s page size base address 0 0 1m byte ba20-ba31 0 1 4m bytes ba22-ba31 1 0 16m bytes ba24-ba31 1 1 reserved ?
49 at91c140 6069a?atarm?05/04 tdf: data float output time bat: byte access mode 0 = byte write mode 1= byte select mode csen: chip select enable 0 = chip select is disabled 1 = chip select is enabled ba: base address this field contains the high-order bits of the base address. if the page size is larger than 1m byte, then the unused bits of the base address are ignored by the smc decoder. smc memory control register register name: smc_mcr access type: read/write drp: data read protocol 0 =standard read mode 1 =early read mode tdf cycles after transfer 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???drp????
50 at91c140 6069a?atarm?05/04 ethernet mac (emac) the at91c140 features two identical ethernet macs, both of which feature the following: compatible with ieee standard 802.3 10 and 100 mbits per second data throughput capability full- and half-duplex operation media independent interface to the physical layer register interface to address, status and control registers dma interface interrupt generation to signal receive and transmit completion 28-byte transmit and 28-byte receive fifos automatic pad and crc generation on transmitted frames address checking logic to recognize four 48-bit addresses supports promiscuous mode where all valid frames are copied to memory supports physical layer management through mdio interface the ethernet mac is the hardware implementation of the mac sub-layer osi reference model between the physical layer (phy) and the logical link layer (llc). it controls the data exchange between a host and a phy layer according to ethernet ieee 802.3 data frame format. the ethernet mac contains the required logic and transmit and receive fifos for dma management. in addition, it is interfaced through mdio/mdc pins for phy layer management. the ethernet mac transfers data in media-independent interface (mii). block diagram figure 20. block diagram ethernet mac interrupt control apb bridge aclk emac irq mx_txclk, mx_rxclk mx_txen, mx_txer mx_crs, mx_col mx_rxer, mx_rxdv mx_rxd[3:0] mx_txd[3:0] dma apb mac asb mx_mdc mx_mdio
51 at91c140 6069a?atarm?05/04 media independe nt interface transmit/receive operation a standard ieee 802.3 packet consists of the following fields: preamble, start of frame delimiter (sfd), destination address (da), source address (sa), length, data (logical link control data) and frame check sequence crc32 (fcs). note: 1. frame length between 64 bytes and 1518 bytes. the packets are manchester-encoded and -decoded and transferred serially using nrz data with a clock. all fields are of fixed length except for the data field. the mac gener- ates and appends the preamble, sfd and crc fields during transmission. the preamble and sfd fields are stripped during reception. preamble and start of frame delimiter (sfd) the preamble field is used to acquire bit synchronization with an incoming packet. when transmitted, each packet contains 62 bits of alternating 1,0 preamble. some of this pre- amble is lost as the packet travels through the network. byte alignment is performed with the start of frame delimiter (sfd) pattern that consists of two consecutive 1's. destination address (da) the destination address (da) indicates the destination of the packet on the network and is used to filter unwanted packets. there are three types of address formats: physical, multicast and broadcast. the physical address is a unique address that corresponds only to a single node. all physical addresses have an msb of 0. multicast addresses begin with an msb of 1. the mac filters multicast addresses using a standard hashing algorithm that maps all multicast addresses into a 6-bit value. this 6-bit value indexes a 64-bit array that filters the value. if the address consists of all ones, it is a broadcast address, indicating that the packet is intended for all nodes. source address (sa) the source address (sa) is the physical address of the node that sent the packet. source addresses cannot be multicast or broadcast addresses. this field is passed to buffer memory. table 17. pin configuration mii signal signal name pin name emac a pin name emac b transmit clock etxck ma_txclk mb_txclk carrier sense ecrs ma_crs mb_crs collision detect ecol ma_col mb_col receive data valid erxdv ma_rxdv mb_rxdv 4-bit receive data erx0-erx3 ma_rxd[0:3] mb_rxd[0:3] receive error erxer ma_rxer mb_rxer receive clock erxck ma_rxclk mb_rxclk transmit enable etxen ma_txen mb_txen 4-bit transmit data etx0-etx3 ma_txd[0:3] mb_txd[0:3] transmit error etxer ma_txer mb_txer table 18. packet format preamble frame (1) alternating 1s/0s sfd da sa length/type llc data pad fcs up to 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 4 bytes
52 at91c140 6069a?atarm?05/04 length/type if the value of this field is less than or equal to 1500, then the length/type field indicates the number of bytes in the subsequent llc data field. if the value of this field is greater than or equal to 1536, then the length/type field indicates the nature of the mac client protocol (protocol type). llc data the data field consists of anywhere from 46 to 1500 bytes. messages longer than 1500 bytes need to be broken into multiple packets. messages shorter than 46 bytes require appending a pad to bring the data field to the minimum length of 46 bytes. if the data field is padded, the number of valid data bytes is indicated in the length field. frame check sequence field (fcs) the frame check sequence (fcs) is a 32-bit crc field, calculated and appended to a packet during transmission to allow detection of errors when a packet is received. dur- ing reception, error free packets result in a specific pattern in the crc generator. packets with improper crc will be rejected. frame format extensions the original ethernet standards define the minimum frame size as 64 bytes and the maximum as 1518 bytes. these numbers include all bytes from the destination mac address field through the frame check sequence field. the preamble and start frame delimiter fields are not included when quoting the size of a frame. the ieee 802.3ac standard extended the maximum allowable frame size to 1522 bytes to allow a vlan tag to be inserted into the ethernet frame format. the big bit defined in the eth_cfg register processes packets with a vlan tag. the vlan protocol permits insertion of an identifier, or tag, into the ethernet frame for- mat to identify the vlan to which the frame belongs. it allows frames from stations to be assigned to logical groups. this provides various benefits, such as easing network administration, allowing formation of work groups, enhancing network security, and pro- viding a means of limiting broadcast domains (refer to ieee standard 802.1q for definition of the vlan protocol). the 802.3ac standard defines only the implementation details of the vlan protocol that are specific to ethernet. if present, the 4-byte vlan tag is inserted into the ethernet frame between the source mac address field and the length field. the first 2 bytes of the vlan tag consist of the ?802.1q tag type? and are always set to a value of 0x8100. the 0x8100 value is a reserved length/type field assignment that indicates the presence of the vlan tag, and signals that the traditional length/type field can be found at an offset of four bytes fur- ther into the frame. the last two bytes of the vlan tag contain the following information. the first three bits are a user priority field that may be used to assign a priority level to the ethernet frame. the following one bit is a canonical format indicator (cfi) used in ethernet frames to indicate the presence of a routing information field (rif). the last twelve bits are the vlan identifier (vid) that uniquely identifies the vlan to which the ethernet frame belongs. with the addition of vlan tagging, the 802.3ac standard permits the maximum length of an ethernet frame to be extended from 1518 bytes to 1522 bytes. table 19 on page 53 illustrates the format of an ethernet frame that has been ?tagged? with a vlan identifier according to the ieee 802.3ac standard.
53 at91c140 6069a?atarm?05/04 dma operations frame data is transferred to and from the ethernet mac via the dma interface. all trans- fers are 32-bit words and may be single accesses or bursts of two, three or four words. burst accesses do not cross 16-byte boundaries. the dma controller performs four types of operations on the asb bus. in order of prior- ity, these operations are receive buffer manager read, receive buffer manager write, transmit data dma read and receive data dma write. transmitter mode transmit frame data needs to be stored in contiguous memory locations. it does not need to be word-aligned. the transmit address register is written with the address of the first byte to be transmitted. transmit is initiated by writing the number of bytes to transfer (length) to the transmit control register. the transmit channel then reads data from memory 32 bits at a time and places them in the transmit fifo. the transmit block starts frame transmission when three words have been loaded into the fifo. the transmit address register must be written before the transmit control register. while a frame is being transmitted, it is possible to set up one other frame for transmission by writing new values to the transmit address and control registers. reading the transmit address register returns the address of the buffer currently being accessed by the trans- mit fifo. reading the transmit control register returns the total number of bytes to be transmitted. the bnq bit in the transmit status register indicates whether another buffer can be safely queued. an interrupt is generated whenever this bit is set. frame assembly starts by adding preamble and the start frame delimiter. data is taken from the transmit fifo word-by-word. if necessary, padding is added to make the frame length 60 bytes. the crc is calculated as a 32-bit polynomial. this is inverted and appended to the end of the frame, making the frame length a minimum of 64 bytes. the crc is not appended if the ncrc bit is set in the transmit control register. in full-duplex mode, frames are transmitted immediately. back-to-back frames are trans- mitted at least 96 bit times apart to guarantee the inter-frame gap. table 19. ethernet frame with vlan tagging preamble 7 bytes start frame delimiter 1 byte dest. mac address 6 bytes source mac address 6 bytes length/type = 802.1q tag type 2 byte tag control information 2 bytes length / type 2 bytes mac client data 0 - n bytes pad 0 - p bytes frame check sequence 4 bytes
54 at91c140 6069a?atarm?05/04 in half-duplex mode, the transmitter checks carrier sense. if asserted, it waits for it to de- assert and then starts transmission after the inter-frame gap of 96 bit-times. if the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retries transmission after the backoff time has elapsed. an error is indicated and any further attempts aborted if 16 attempts cause collisions. if transmit dma underruns, bad crc is automatically appended using the same mecha- nism as jam insertion. underrun also causes txer to be asserted. receiver mode when a packet is received, it is checked for valid preamble, crc, alignment, length and address. if all these criteria are met, the packet is stored successfully in a receive buffer. if at the end of reception the crc is bad, then the received buffer is recovered. each received frame including crc is written to a single receive buffer. receive buffers are word-aligned and are capable of containing 1518 or 1522 bytes (big = 1 in eth_cfg) of data (the maximum length of an ethernet frame). the start location for each received frame is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. each entry in the list consists of two words. the first word is the address of the received buffer; the second is the receive status. table 20 defines an entry in the received buffer descriptor list. to receive frames, the buffer queue must be initialized by writing an appropriate address to bits [31:2] in the first word of each list entry. bit zero of word zero must be written with zero. after a frame is received, bit zero becom es set and the second word indicates what caused the frame to be copied to memory. the start location of the received buffer descriptor list should be written to the received buffer queue pointer register before receive is enabled (by setting the receive enable bit in the network control register). as soon as the received block starts writing re ceived frame data to the receive fifo, the received buffer manager reads the first receive buffer location pointed to by the received buffer queue pointer register. if the filter block is active, the frame should be copied to memory; the receive data dma operation starts writing data into the receive buffer. if an error occurs, the buffer is recovered. if the frame is received without error, the queue entry is updated. the buffer pointer is rewritten to memory with its low-order bit set to indicate successful frame reception and a used buffer. the next word is written with the length of the frame and how the destination address was recognized. the next receive buffer location is then read from the following word or, if the current buffer pointer had its wrap bit set, the beginning of the table. the maximum number of buffer pointers before a wrap bit is seen is 1024. if a wrap bit is not seen by then, a wrap bit is assumed in that entry. the received buffer queue pointer register must be written with zero in its lower- order bit positions to enable the wrap function to work correctly. if bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. in this case, the dma block sets the buffer unavailable bit in the received status register and triggers an interrupt. the frame is discarded and the queue entry is reread on reception of the next frame to see if the buffer is now available. each discarded frame increments a statistics register that is cleared on being read. when there is network congestion, it is possible for the mac to be programmed to apply back pressure. this is when half-duplex mode collisions are forced on all received frames by transmit- ting 64 bits of data (a default pattern).
55 at91c140 6069a?atarm?05/04 reading the received buffer queue register returns the location of the queue entry cur- rently being accessed. the queue wraps around to the start after either 1024 entries (i.e., 2048 words) or when the wrap bit is found to be set in bit 1 of the first word of an entry. address checking whether or not a frame is stored depends on what is enabled in the network configura- tion register, the contents of the specific address and hash registers and the frame destination address. in this implementation of the mac the frame source address is not checked. a frame is not copied to memory if the ma c is transmitting in half-duplex mode at the time a destination address is received. the hash register is 64 bits long and takes up two locations in the memory map. there are four 48-bit specific address registers, each taking up two memory locations. the first location contains the first four bytes of the address; the second location con- tains the last two bytes of the address stored in its least significant byte positions. the addresses stored can be specific, group, local or universal. ethernet frames are transmitted a byte at a time, lsb first. the first bit (i.e., the lsb of the first byte) of the destination address is the group/individual bit and is set one for mul- ticast addresses and zero for unicast. this bit corresponds to bit 24 of the first word of table 20. received buffer descriptor list bit function word 0 31:2 base address of receive buffer 1 wrap bit. if this bit is set, the counter that is ored with the received buffer queue pointer register to give the pointer to entries in this table is cleared after the buffer is used. 0 ownership bit. 1 indicates software owns the pointer, 0 indicates that the dma owns the buffer. if this bit is not zero when the entry is read by the receiver, the buffer unavailable bit is set in the received status register and the receiver goes inactive. word 1 31 global all ones broadcast address detected 30 multicast hash match 29 unicast hash match 28 external address 27 unknown source address (reserved for future use) 26 local address match (specific address 1 match) 25 local address match (specific address 2 match) 24 local address match (specific address 3 match) 23 local address match (specific address 4 match) 22:11 reserved; written to 0 10:0 length of frame including fcs
56 at91c140 6069a?atarm?05/04 the specific address register. the msb of the first byte of the destination address corre- sponds to bit 31 of the specific address register. the specific address registers are compared to the destination address of received frames once they have been activated. addresses are deactivated at reset or when the first byte [47:40] is written and activated or when the last byte [7:0] is written. if a receive frame address matches an active address, the local match signal is set and the store frame pulse signal is sent to the dma block via the aclk synchronization block. a frame can also be copied if a unicast or multicast hash match occurs, it has the broad- cast address of all ones, or the copy all frames bit in the network configuration register is set. the broadcast address of 0xffffffff is recognized if the no broadcast bit in the net- work configuration register is zero. this sets the broadcast match signal and triggers the store frame signal. the unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matc hed frames. so all multicast frames can be received by setting all bits in the hash register. the crc algorithm reduces the destination address to a 6-bit index into a 64-bit hash register.if the equivalent bit in the register is set, the frame is matched depending on whether the frame is multicast or unicast and the appropriate match signals are sent to the dma block. if the copy all frames bit is set in the network configuration register, the store frame pulse is always sent to the dma block as soon as any destination address is received.
57 at91c140 6069a?atarm?05/04 emac user interface maca memory address: 0xff034000 macb memory address: 0xff038000 note: 1. for further details on the statistics registers, see table 22, ?statistics register block,? on page 71. table 21. ethernet mac register mapping offset register name register description read/write reset 0x00 eth_ctl network control register read/write 0x0 0x04 eth_cfg network configuration register read/write 0x800 0x08 eth_sr network status register read-only 0x6 0x0c eth_tar transmit address register read/write 0x0 0x10 eth_tcr transmit control register read/write 0x0 0x14 eth_tsr transmit status register read/write 0x18 0x18 eth_rbqp receive buffer queue pointer read/write 0x0 0x1c ? reserved read-only 0x0 0x20 eth_rsr receive status register read/write 0x0 0x24 eth_isr interrupt status register read/write 0x0 0x28 eth_ier interrupt enable register write-only ? 0x2c eth_idr interrupt disable register write-only ? 0x30 eth_imr interrupt mask register read-only 0xfff 0x34 eth_man phy maintenance register read/write 0x0 statistics registers (1) 0x40 eth_fra frames transmitted ok register read/write 0x0 0x44 eth_scol single collision frame register read/write 0x0 0x48 eth_mcol multiple collision frame register read/write 0x0 0x4c eth_ok frames received ok register read/write 0x0 0x50 eth_seqe frame check sequence error register read/write 0x0 0x54 eth_ale alignment error register read/write 0x0 0x58 eth_dte deferred transmission frame register read/write 0x0 0x5c eth_lcol late collision register read/write 0x0 0x60 eth_ecol excessive collision register read/write 0x0 0x64 eth_cse carrier sense error register read/write 0x0 0x68 eth_tue transmit underrun error register read/write 0x0 0x6c eth_cde code error register read/write 0x0 0x70 eth_elr excessive length error register read/write 0x0 0x74 eth_rjb receive jabber register read/write 0x0 0x78 eth_usf undersize frame register read/write 0x0 0x7c eth_sqee sqe test error register read/write 0x0 0x80 eth_drfc discarded rx frame register read/write 0x0 address registers 0x90 eth_hsh hash address high [63:32] read/write 0x0 0x94 eth_hsl hash address low [31:0] read/write 0x0 0x98 eth_sa1l specific address 1 low, first 4 bytes read/write 0x0 0x9c eth_sa1h specific address 1 high, last 2 bytes read/write 0x0 0xa0 eth_sa2l specific address 2 low, first 4 bytes read/write 0x0 0xa4 eth_sa2h specific address 2 high, last 2 bytes read/write 0x0 0xa8 eth_sa3l specific address 3 low, first 4 bytes read/write 0x0 0xac eth_sa3h specific address 3 high, last 2 bytes read/write 0x0 0xb0 eth_sa4l specific address 4 low, first 4 bytes read/write 0x0 0xb4 eth_sa4h specific address 4 high, last 2 bytes read/write 0x0
58 at91c140 6069a?atarm?05/04 emac control register register name: eth_ctl access type: read/write lb: loopback . when set, loopback signal is at high level. lbl: loopback local when set, connects etx[3:0] to erx[3:0], etxen to erxd v, forces full duplex and drives erxck and etxck_refck with ack divided by 4. re: receive enable when set, enables the ethernet mac to receive data. te: transmit enable when set, enables the ethernet transmitter to send data. mpe: management port enable set to one to enable the management port. when zero, forces mdio to high impedance state. csr: clear statistics registers this bit is write-only. writing a one clears the statistics registers. isr: increment statistics registers this bit is write-only. writing a one increments all the statistics registers by one for test purposes. wes: write enable for statistics registers setting this bit to one makes the statistics registers writable for functional test purposes. bp: back pressure if this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (de fault pattern). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????bp 76543210 wes isr csr mpe te re lbl lb
59 at91c140 6069a?atarm?05/04 emac mode register name: eth_cfg access type: read/write spd: speed set to 1 to indicate 100 mbit/sec, 0 for 10 mbit/sec. has no other functional effect. fd: full duplex if set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. br: bit rate caf: copy all frames when set to 1, all valid frames are received. nbc: no broadcast when set to 1, frames addressed to the broadcast address of all ones are not received. mti: multicast hash enable when set multicast frames are received when six bits of the crc of the destination address point to a bit that is set in the hash register. uni: unicast hash enable when set, unicast frames are received when six bits of the crc of the destination address point to a bit that is set in the hash register. big: receive 1522 bytes when set, the mac receives up to 1522 bytes. normally the mac receives frames up to 1518 bytes in length. this bit allows to receive extended ethernet frame with ?vlan tag? (ieee 802.3ac) eae: external address match enable clk the arm clock is divided down to generate mdc (the clock for the mdio). to conform with ieee standard 802.3 mdc must not exceed 2.5 mhz. at reset this field is set to 10 so that ack is divided by 32. rty: retry test when set, the time between frames is always one time slot. for test purposes only. must be cleared for normal operation. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? rty clk eae big 76543210 uni mti nbc caf ? br fd spd clk mdc 00 ack divided by 8 01 ack divided by 16 10 ack divided by 32 11 ack divided by 64
60 at91c140 6069a?atarm?05/04 emac status register name: eth_sr access type: read-only link 0 = link is at 0. 1 = link is at 1. mdio 0 = mdio pin not set. 1 = mdio pin set. idle 0 = phy logic is idle. 1 = phy logic is running. emac transmit address register name: eth_tar access type: read/write address: transmit address register written with the address of the frame to be transmitted, read as the base address of the buffer being accessed by the trans- mit fifo. note that if the two least significant bits are not zero, transmit starts at the byte indicated. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????idlemdiolink 31 30 29 28 27 26 25 24 address 23 22 21 20 19 18 17 16 address 15 14 13 12 11 10 9 8 address 76543210 address
61 at91c140 6069a?atarm?05/04 emac transmit control register name: eth_tcr access type: read/write len: transmit frame length this register is written to the number of bytes to be transmitted excluding the four crc bytes unless the no crc bit is asserted. writing these bits to any non-zero value initiates a transmission. if the value is greater than 1514 (1518 if no crc is being generated), an oversize frame is transmitted. this field is buffered so that a new frame can be queued while the previous frame is still being transmitted. must always be written in address-then-length order. reads as the total number of bytes to be transmitted (i.e., this value does not change as the frame is transmitted.) frame transmission does not start until two 32-bit words have been loaded into the transmit fifo. the length must be great enough to ensure two words are loaded. ncrc: no crc if this bit is set, it is assumed that the crc is included in the length being written in the low-order bits and the mac does n ot append crc to the transmitted frame. if the buffer is not at least 64 bytes long, a short frame is sent. this field is buffered so that a new frame can be queued while the previous frame is still being transmitted. reads as the value of the frame cur- rently being transmitted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ncrc ? ? ? ? len 76543210 len
62 at91c140 6069a?atarm?05/04 emac transmit status register name: eth_tsr access type: read/write ovr: ethernet transmit buffer overrun software has written to the transmit address register (eth_tar) or transmit control register (eth_tcr) when bit bnq was not set. cleared by writing a one to this bit. col: collision occurred set by the assertion of a collision. cleared by writing a one to this bit. rle: retry limit exceeded cleared by writing a one to this bit. idle: transmitter idle asserted when the transmitter has no frame to transmit. cleared when a length is written to transmit frame length portion of the transmit control register. this bit is read-only. bnq: ethernet transmit buffer not queued software may write a new buffer address and length to the transmit dma controller when set. cleared by having one frame ready to transmit and another in the process of being transmitted. this bit is read-only. comp: transmit complete set when a frame has been transmitted. cleared by writing a one to this bit. und: transmit underrun set when transmit dma was not able to read data from memory in time. if this happens, the transmitter forces bad crc. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? und comp bnq idle rle col ovr
63 at91c140 6069a?atarm?05/04 emac receive buffer queue pointer register name: eth_rbqp access type: read/write address: receive buffer queue pointer written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. the receive buffer is forced to word alignment. emac receive status register name: eth_rsr access type: read/write bna: buffer not available an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. the dma rereads the pointer each time a new frame starts until a valid pointer is found. this bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. cleared by writing a one to this bit. rec: frame received one or more frames have been received and placed in memory. cleared by writing a one to this bit. ovr: rx overrun the dma block was unable to store the receive frame to memory, either because the mac asb bus was not granted in time or because an abort occurred. the buffer is recovered if this happens. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 address 23 22 21 20 19 18 17 16 address 15 14 13 12 11 10 9 8 address 76543210 address 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????ovrrecbna
64 at91c140 6069a?atarm?05/04 emac interrupt status register name: eth_isr access type: read/write done: management done the phy maintenance register has completed its operation. cleared on read. rcom: receive complete a frame has been stored in memory. cleared on read. rbna: receive buffer not available cleared on read. tovr: transmit buffer overrun software has written to the transmit address register (eth_tar) or transmit control register (eth_tcr) when bnq of the transmit status register (eth_tsr) was not set. cleared on read. tund: transmit buffer underrun ethernet transmit buffer underrun. the transmit dma did not complete fetch frame data in time for it to be transmitted. cleared on read. rtry: retry limit retry limit exceeded. cleared on read. tbre: transmit buffer register empty software may write a new buffer address and length to the transmit dma controller. cleared by having one frame ready to transmit and another in the process of being transmitted. cleared on read. tcom: transmit complete set when a frame has been transmitted. cleared on read. tidle: transmit idle set when all frames have been transmitted. cleared on read. link set when link pin changes value. rovr: rx overrun set when the rx overrun status bit is set. cleared on read. abt: abort set when the dma generates an abort. cleared on read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? abt rovr link tidle 76543210 tcom tbre rtry tund tovr rbna rcom done
65 at91c140 6069a?atarm?05/04 emac interrupt enable register name: eth_ier access type: write-only done: management done interrupt enable rcom: receive complete interrupt enable rbna: receive buffer not available interrupt enable tovr: transmit buffer overrun interrupt enable tund: transmit buffer underrun interrupt enable rtry: retry limit interrupt enable tbre: transmit buffer register empty interrupt enable tcom: transmit complete interrupt enable tidle: transmit idle interrupt enable link: link interrupt enable rovr: rx overrun interrupt enable abt: abort interrupt enable 0 =no effect. 1 =enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? abt rovr link tidle 76543210 tcom tbre rtry tund tovr rbna rcom done
66 at91c140 6069a?atarm?05/04 emac interrupt disable register name: eth_idr access type: write-only done: management done interrupt disable rcom: receive complete interrupt disable rbna: receive buffer not available interrupt disable tovr: transmit buffer overrun interrupt disable tund: transmit buffer underrun interrupt disable rtry: retry limit interrupt disable tbre: transmit buffer register empty interrupt disable tcom: transmit complete interrupt disable tidle: transmit idle interrupt disable link: link interrupt disable rovr: rx overrun interrupt disable abt: abort interrupt disable 0 =no effect. 1 =disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? abt rovr link tidle 76543210 tcom tbre rtry tund tovr rbna rcom done
67 at91c140 6069a?atarm?05/04 emac interrupt mask register name: eth_imr access type: read-only done: management done interrupt mask rcom: receive complete interrupt mask rbna: receive buffer not available interrupt mask tovr: transmit buffer overrun interrupt mask tund: transmit buffer underrun interrupt mask rtry: retry limit interrupt mask tbre: transmit buffer register empty interrupt mask tcom: transmit complete interrupt mask tidle: transmit idle interrupt mask link: link interrupt mask rovr: rx overrun interrupt mask abt: abort interrupt mask 0 =the corresponding interrupt is enabled. 1 =the corresponding interrupt is not enabled. important note: the interrupt is disabled when the corresponding bit is set. this is non-standard with other peripherals of the product, as generally a mask bit set enables the interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? abt rovr link tidle 76543210 tcom tbre rtry tund tovr rbna rcom done
68 at91c140 6069a?atarm?05/04 emac phy maintenance register name: eth_man access type: read/write writing to this register starts the shift register that controls the serial connection to the phy. on each shift cycle the mdio pin becomes equal to the msb of the shift register and lsb of the shift register becomes equal to the value of the mdio pin. when the shifting is complete an interrupt is generated and the idle field is set in the network status register. when read, gives current shifted value. data for a write operation this is written with the data to be written to the phy. after a read operation this contains the data rea d from the phy. code must be written to 10 in accordance with ieee standard 802.3. reads as written. rega register address. specifies the register in the phy to access. phya phy address. normally is 0. rw read/write operation. 10 is read. 01 is write. any other value is an invalid phy management frame. high must be written with 1 to make a valid phy management frame. conforms with ieee standard 802.3. low must be written with 0 to make a valid phy management frame. conforms with ieee standard 802.3. 31 30 29 28 27 26 25 24 low high rw phya 23 22 21 20 19 18 17 16 phya rega code 15 14 13 12 11 10 9 8 data 76543210 data
69 at91c140 6069a?atarm?05/04 emac hash address high register register name: eth_hsh access type: read/write addr hash address bits 63 to 32. emac hash address low register register name: eth_hsl access type: read/write addr hash address bits 31 to 0. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
70 at91c140 6069a?atarm?05/04 emac specific address (1, 2, 3 and 4) high register register name: eth_sa1h,...eth_sa4h access type: read/write addr unicast addresses (1, 2, 3 and 4), bits 47:32. emac specific address (1, 2, 3 and 4) low register register name: eth_sa1l,...eth_sa4l access type: read/write addr unicast addresses (1, 2, 3 and 4), bits 31:0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
71 at91c140 6069a?atarm?05/04 emac statistics register block registers these registers reset to zero on a read and remain at all ones when they count to their maximum value. they should be read frequently enough to prevent loss of data. the statistics register block contains the registers found in table 21, ?ethernet mac register mapping,? on page 57. table 22. statistics register block register register name description frames transmitted ok register eth_fra a 24-bit register counting the number of frames successfully transmitted. single collision frame register eth_scol a 16-bit register counting the number of frames experiencing a single collision before being transmitted and experiencing no carrier loss nor underrun. multiple collision frame register eth_mcol a 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no underrun). frames received ok register eth_ok a 24-bit register counting the number of good frames received, i.e., address recognized. a good frame is of length 64 to 1518 bytes and has no fcs, alignment or code errors. frame check sequence error register eth_seqe an 8-bit register counting address-recognized frames that are an integral number of bytes long, that have bad crc and that are 64 to 1518 bytes long. alignment error register eth_ale an 8-bit register counting frames that: - are address-recognized, - are not an integral number of bytes long, - have bad crc when their length is truncated to an integral number of bytes, - are between 64 and 1518 bytes long. deferred transmission frame register eth_dte a 16-bit register counting the number of frames experiencing deferral due to carrier sense active on their first attempt at transmission (no underrun or collision). late collision register eth_lcol an 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. no carrier loss or underrun. a late collision is counted twice, i.e., both as a collision and a late collision. excessive collision register eth_ecol an 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions (64 - 1518 bytes, no carrier loss or underrun). carrier sense error register eth_cse an 8-bit register counting the number of frames for which carrier sense was not detected and that were maintained in half-duplex mode one slot time (512 bits) after the start of transmission (no excessive collision). transmit underrun error register eth_tue an 8-bit register counting the number of frames not transmitted due to a transmit dma underrun. if this register is incremented, then no other register is incremented. code error register eth_cde an 8-bit register counting the number of frames that are address-recognized, had rxer asserted during reception. if this counter is incremented, then no other counters are incremented. excessive length error register eth_elr an 8-bit register counting the number of frames received exceeding 1518 bytes in length but that do not have either a crc error, an alignment error or a code error. receive jabber register eth_rjb an 8-bit register counting the number of frames received exceeding 1518 bytes in length and having either a crc error, an alignment error or a code error. undersize frame register eth_usf an 8-bit register counting the number of frames received that are less than 64 bytes in length but that do not have either a crc error, an alignment error or a code error. sqe test error register eth_sqee an 8-bit register counting the number of frames where pin ecol was not asserted within a slot time of pin etxen being deasserted. discarded rx frame register eth_drfc this 16-bit counter is incremented every time an address-recognized frame is received but cannot be copied to memory because the receive buffer is available.
72 at91c140 6069a?atarm?05/04 advanced interrupt controller (aic) the at91c140 integrates the atmel advanced interrupt controller (aic). the interrupt controller is connected to the fast interrupt request (nfiq) and the stan- dard interrupt request (nirq) inputs of the arm7tdmi processor. the processor?s nfiq line can only be asserted by the external fast interrupt request input (fiq). the nirq line can be asserted by the interrupts generated by the on-chip peripherals and the two external interrupt request lines, irq0 to irq1. an 8-level priority encoder allows the user to define the priority between the different interrupt sources. internal sources are programmed to be level-sensitive or edge-trig- gered. external sources can be programmed to be positive- or negative-edge triggered or high- or low-level sensitive. figure 21. advanced interrupt controller block diagram control logic memorization memorization prioritization controller nirq manager nfiq manager fiq source advanced peripheral bus (apb) arm7tdmi core nfiq nirq internal interrupt sources external interrupt sources table 23. interrupt sources interrupt source interrupt name interrupt description 0 fiq fast interrupt (lowp) 1-- 2 swi software interrupt 3 uarta uart a interrupt 4 tc0 timer channel 0 interrupt 5 tc1 timer channel 1 interrupt 6 tc2 timer channel 2 interrupt 7 pioa pio a interrupt 8 maca mac a interrupt 9 spi serial peripheral interface 10 irq0 external interrupt
73 at91c140 6069a?atarm?05/04 priority controller the nirq line is controlled by an 8-level priority encoder. each source has a program- mable priority level of 7 to 0. level 7 is the highest priority and level 0 the lowest. when the aic receives more than one unmasked interrupt at a time, the interrupt with the highest priority is serviced first. if both interrupts have equal priority, the interrupt with the lowest interrupt source number is serviced first. the current priority level is defined as the priority level of the current interrupt at the time the register aic_ivr is read (the interrupt which will be serviced). in the case when a higher priority unmasked interrupt occurs while an interrupt already exists, there are two possible outcomes depending on whether the aic_ivr has been read. 1. if the nirq line has been asserted but the aic_ivr has not been read, then the processor will read the new higher priority interrupt handler number in the aic_ivr register and the current interrupt level is updated. 2. if the processor has already read the aic_ivr, then the nirq line is reasserted. when the processor has authorized nested interrupts to occur and reads the aic_ivr again, it reads the new, higher priority interrupt handler address. at the same time the current priority value is pushed onto a first-in last-out stack and the current priority is updated to the higher priority. when the end of interrupt command register (aic_eoicr) is written, the current inter- rupt level is updated with the current interrupt level from the stack (if any). hence, at the end of a higher priority interrupt, the aic returns to the previous state corresponding to the preceding lower priority interrupt which had been interrupted. interrupt handling the interrupt handler must read the aic_ivr as soon as possible. this deasserts the nirq request to the processor and clears the interrupt in case it is programmed to be edge-triggered. this permits the aic to assert the nirq line again when a higher priority unmasked interrupt occurs. at the end of the interrupt service routine, the end of interrupt command register (aic_eoicr) must be written. this allows pending interrupts to be serviced. interrupt masking each interrupt source, including fiq, can be enabled or disabled using the command registers aic_iecr and aic_idcr. the interrupt mask can be read in the read only register aic_imr. a disabled interrupt does not affect the servicing of other interrupts. interrupt clearing and setting all interrupt sources which are programmed to be edge-triggered (including fiq) can be individually set or cleared by respectively writing to the registers aic_iscr and aic_iccr. this function of the interrupt controller is available for auto-test or software debug purposes. 11 irq1 external interrupt 12 reserved 13 macb mac b interrupt 14 uartb uart b interrupt 15 piob pio b interrupt 16 - 31 reserved table 23. interrupt sources (continued) interrupt source interrupt name interrupt description
74 at91c140 6069a?atarm?05/04 standard interrupt sequence it is assumed that: the advanced interrupt controller has been programmed, aic_svr registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. when nirq is asserted and if the i bit of cpsr is 0, the sequence is as follows: 1. the cpsr is stored in spsr_irq, the current value of the program counter is loaded in the irq link register (r14_irq) and the program counter (r15) is loaded with 0x18. in the following cycle during fetch at address 0x1c, the arm core adjusts r14_irq, decrementing it by 4. 2. the arm core enters irq mode if it is not already. 3. when the instruction at 0x18 is executed, the program counter is loaded with the value read in the aic_ivr. reading the aic_ivr has the following effects: sets the current interrupt to be the pending one with the highest priority. the current level is the priority level of the current interrupt. de-asserts the nirq line on the processor (even if vectoring is not used, aic_ivr must be read in order to de-assert nirq). automatically clears the interrupt if it has been programmed to be edge-triggered. pushes the current level on to the stack. returns the aic_svr corresponding to the current interrupt. 4. the previous step establishes a connection to the corresponding isr. this begins by saving the link register (r14_irq) and the spsr (spsr_irq). note that the link register must be decremented by 4 when it is saved if it is to be restored directly into the program counter at the end of the interrupt. 5. further interrupts can then be unmasked by clearing the i bit in the cpsr, allow- ing re-assertion of the nirq to be taken into account by the core. this can occur if an interrupt with a higher priority than the current one occurs. 6. the interrupt handler then proceeds as required, saving the registers which are used and restoring them at the end. during this phase, an interrupt of priority higher than the current level will restart the sequence from step 1. note that if the interrupt is programmed to be level-sensitive, the source of the interrupt must be cleared during this phase. 7. the i bit in the cpsr must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. the service routine should then connect to the common exit routine. 9. the end of interrupt command register (aic_eoicr) must be written in order to indicate to the aic that the current interrupt is finished. this causes the cur- rent level to be popped from the stack, restoring the previous current level if one exists. if another interrupt with lower or equal priority than the old current level is pending, the nirq line is re-asserted but the interrupt sequence does not imme- diately start because the i bit is set in the core. 10. the spsr (spsr_irq) is restored. finally, the saved value of the link register is restored directly into the pc. this has the effect of returning from the interrupt to the step previously executed, of loading the cpsr with the stored spsr and of masking or unmasking the interrupts depending on the state saved in the spsr (the previous state of the arm core). note: the i bit in the spsr is significant. if it is set, it indicates that the arm core was just about to mask irq interrupts when the mask instruction was interrupted. hence, when the spsr is restored, the mask instruction is completed (irq is masked).
75 at91c140 6069a?atarm?05/04 fast interrupt the external fiq line is the only source whic h can raise a fast interrupt request to the processor. therefore it has no priority controller. it can be programmed to be positive- or negative-edge triggered or high- or low-level sensitive in the aic_smr0 register. the fast interrupt handler address can be stored in the aic_svr0 register. the value written into this register is available by reading the aic_fvr register when an fiq inter- rupt is raised. by storing the following instruction at address 0x0000001c, the processor will load the program counter with the interrupt handler address stored in the aic_fvr register. ldr pc, [pc, #-&f20] alternatively, the interrupt handler can be stored starting from address 0x0000001c as described in the arm7tdmi datasheet. fast interrupt sequence it is assumed that: the advanced interrupt controller has been programmed, aic_svr[0] is loaded with the fast interrupt service routine address and the fast interrupt is enabled. nested fast interrupts are not needed by the user. when nfiq is asserted, if the f bit of cpsr is 0, the sequence is: 1. the cpsr is stored in spsr_fiq, the current value of the program counter is loaded in the fiq link register (r14_fiq) and the program counter (r15) is loaded with 0x1c. in the following cycle, during fetch at address 0x20, the arm core adjusts r14_fiq, decrementing it by 4. 2. the arm core enters fiq mode. 3. when the instruction loaded at address 0x1c is executed, the program counter is loaded with the value read in aic_fvr. reading the aic_fvr has the effect of clearing the fast interrupt (source 0 connected to the fiq line) if it has been programmed to be edge-triggered. in this case only, it de-asserts the nfiq line on the processor. 4. the previous step establishes a connection to the corresponding interrupt ser- vice routine. it is not necessary to save the link register (r14_fiq) and the spsr (spsr_fiq) if nested fast interrupts are not needed. 5. the interrupt handler can then proceed as required. it is not necessary to save registers r8 to r13 because fiq mode has its own dedicated registers and the user r8 to r13 are banked. the other registers, r0 to r7, must be saved before being used and restored at the end (before the next step). note that if the fast interrupt is programmed to be level- sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the nfiq line. 6. finally, the link register (r14_fiq) is restored into the pc after decrementing it by 4 (e.g., with instruction sub pc, lr, #4). this has the effect of returning from the interrupt to the step previously executed, of loading the cpsr with the spsr and of masking or unmasking the fast interrupt depending on the state saved in the spsr. note: the f bit in the spsr is significant. if it is set, it indicates that the arm core was just about to mask fiq interrupts when the mask instruction was interrupted. hence, when the spsr is restored, the interrupted instruction is completed (fiq is masked). software interrupt any interrupt source of the aic can be a software interrupt. it must be programmed to be edge-triggered in order to set or clear it by writing to the aic_iscr and aic_iccr. this is totally independent of the swi instruction of the arm7tdmi processor.
76 at91c140 6069a?atarm?05/04 spurious interrupt a spurious interrupt is a signal of very short duration on one of the interrupt input lines. a spurious interrupt also arises when an interrupt is triggered and masked in the same cycle. spurious interrupt sequence a spurious interrupt is handled by the following sequence of actions. 1. when an interrupt is active, the aic asserts the nirq (or nfiq) line and the arm7tdmi enters irq (or fiq) mode. at this moment, if the interrupt source disappears, the nirq (or nfiq) line is de-asserted but the arm7tdmi continues with the interrupt handler. 2. if the irq vector register (aic_ivr) is read when the nirq is not asserted, the aic_ivr is read with the contents of the spurious interrupt vector register. 3. if the fiq vector register (aic_fvr) is read when the nfiq is not asserted, the aic_fvr is read with the contents of the spurious interrupt vector register. 4. the spurious isr must write an end of interrupt command as a minimum, how- ever, it is sufficient to write to the end of interrupt command register (aic_eoicr). until the aic_eoicr write is received by the interrupt controller, the nirq (or nfiq) line is not re-asserted. 5. this causes the arm7tdmi to jump into the spurious interrupt routine. 6. during a spurious isr, the aic_isr reads 0.
77 at91c140 6069a?atarm?05/04 aic user interface base address: 0xff030000 with double mapping at address 0xffff f000 note: 1. the reset value of this register depends on the level of the external irq lines. all other sources are cleared at reset. table 1. aic register mapping offset register register name access reset state 0x000 0x004 ? 0x07c source mode register 0 source mode register 1 ? source mode register 31 aic_smr0 aic_smr1 ? aic_smr31 read/write read/write ? read/write 0 0 ? 0 0x080 0x084 ? 0xfc0 source vector register 0 source vector register 1 ? source vector register 31 aic_svr0 aic_svr1 ? aic_svr31 read/write read/write ? read/write 0 0 ? 0 0x100 0x104 0x108 0x10c irq vector register fiq vector register interrupt status register interrupt pending register aic_ivr aic_fvr aic_isr aic_ipr read-only read-only read-only read-only 0 0 0 (1) 0x110 0x114 0x118 0x11c interrupt mask register core interrupt status register reserved reserved aic_imr aic_cisr ? ? read-only read-only ? ? 0 0 ? ? 0x120 0x124 0x128 0x12c interrupt enable command register interrupt disable command register interrupt clear command register interrupt set command register aic_iecr aic_idcr aic_iccr aic_iscr write-only write-only write-only write-only ? ? ? ? 0x130 end-of-interrupt command register aic_eoicr write-only ? 0x134 spurious interrupt vector register aic_spu read/write 0
78 at91c140 6069a?atarm?05/04 aic source mode register register name: aic_smr0...aic_smr31 access type: read/write prior: priority level programs the priority level for all sources except source 0 (fiq). the priority level can be between 0 (lowest) and 7 (highest). the priority level is not used for the fiq in the smr0. srctype: interrupt source type programs the input to be positive- or negative-edge triggered or positive- or negative-level sensitive. the active level or edge is not programmable for the internal sources. aic source vector registers register name: aic_svr0...aic_svr31 access type: read/write vector in these registers, the user may store the addresses of the corresponding handler for each interrupt source. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? srctype ? ? prior srctype internal sources external sources 00 level-sensitive low-level sensitive 01 edge-triggered negative-edge triggered 10 level-sensitive high-level sensitive 11 edge-triggered positive-edge triggered 31 30 29 28 27 26 25 24 vector 23 22 21 20 19 18 17 16 vector 15 14 13 12 11 10 9 8 vector 76543210 vector
79 at91c140 6069a?atarm?05/04 aic interrupt vector registers register name: aic_ivr access type: read-only reset value: 0 irqv the irq vector register contains the vector programmed by the user in the source vector register corresponding to the current interrupt. the svr register (1 to 31) is indexed by the current interrupt number when the ivr register is read. when there is no interrupt, the irq register reads 0. aic fiq vector register register name: aic_fvr access type: read-only reset value: 0 fiq the vector register contains the vector programmed by the user in svr register 0 which corresponds to fiq. 31 30 29 28 27 26 25 24 irqv 23 22 21 20 19 18 17 16 irqv 15 14 13 12 11 10 9 8 irqv 76543210 irqv 31 30 29 28 27 26 25 24 fiqv 23 22 21 20 19 18 17 16 fiqv 15 14 13 12 11 10 9 8 fiqv 76543210 fiqv
80 at91c140 6069a?atarm?05/04 aic interrupt st atus register register name: aic_isr access type: read-only irqid the interrupt status register returns the current interrupt source register. aic interrupt pending register register name: aic_ipr access type: read-only interrupt pending 0 = corresponding interrupt is not pending. 1 = corresponding interrupt is pending. aic interrupt mask register register name: aic_imr access type: read-only interrupt mask 0 = corresponding interrupt is disabled. 1 = corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??? irqid 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 piob uartb macb 0 irq1 irq0 spi maca 76543210 pioa tc2 tc1 tc0 uarta swi 0 fiq 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 piob uartb macb 0 irq1 (1) irq0 spi maca 76543210 pioa tc2 tc1 tc0 uarta swi 0 fiq
81 at91c140 6069a?atarm?05/04 aic core interrupt status register register name: aic_cisr access type: read-only nfiq: nfiq status 0 = nfiq line inactive. 1 = nfiq line active. nirq: nirq status 0 = nirq line inactive. 1 = nirq line active. aic interrupt enable command register register name: aic_iecr access type: write-only interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????nirqnfiq 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 piob uartb macb 0 irq1 irq0 spi maca 76543210 pioa tc2 tc1 tc0 uarta swi 0 fiq
82 at91c140 6069a?atarm?05/04 aic interrupt disable command register register name: aic_idcr access type: write-only interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. aic interrupt clear command register register name: aic_iccr access type: write-only interrupt clear 0 = no effect. 1 = clears the corresponding interrupt. 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 piob uartb macb 0 irq1 irq0 spi maca 76543210 pioa tc2 tc1 tc0 uarta swi 0 fiq 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 piob uartb macb 0 irq1 irq0 spi maca 76543210 pioa tc2 tc1 tc0 uarta swi 0 fiq
83 at91c140 6069a?atarm?05/04 aic interrupt set command register register name: aic_iscr access type: write-only interrupt set 0 = no effect. 1 = sets the corresponding interrupt. a ic end of interrupt command register register name: aic_eoicr access type: write-only the end of interrupt command register is used by the interrupt routine to indicate that the interrupt treatment is complete. any value can be written as it is only necessary to make a write to this register location to signal the end of interrupt treatment. 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 piob uartb macb 0 irq1 irq0 spi maca 76543210 pioa tc2 tc1 tc0 uarta swi 0 fiq 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????????
84 at91c140 6069a?atarm?05/04 aic spurious interr upt vector register register name: aic_spu access type: read/write siqv this register contains the 32-bit address of an interrupt routine which is used to treat cases of spurious interrupts. the programmed address is read in the aic_ivr if it is read when the nirq line is not asserted. the programmed address is read in the aic_fvr if it is read when the nfiq line is not asserted. 31 30 29 28 27 26 25 24 siqv 23 22 21 20 19 18 17 16 siqv 15 14 13 12 11 10 9 8 siqv 76543210 siqv
85 at91c140 6069a?atarm?05/04 parallel i/o controller (pio) the at91c140 integrates two pio controllers, pioa and piob. pioa controls 32 i/o lines and piob controls 16 fi/o lines. each i/o line can be programmed as an input or an output and can generate an interrupt on level change. these pins are used for several functions: external i/o for internal peripherals keypad controller function general purpose i/o output selection the user can enable each individual i/o signal as an output with the pio_oer and pio_odr registers. the output status of the i/o signals can be read in the pio_osr register. the direction defined has an effect only if the pin is configured to be controlled by the pio controller. i/o levels each pin can be configured to be driven high or low. the level is defined in four different ways, according to the following conditions: if a pin is controlled by the pio controller and is defined as an output, the level is programmed using the pio_sodr and pio_codr registers. in this case, the programmed value can be read in the pio_odsr register. if a pin is controlled by the pio controller and is not defined as an output, the level is determined by the external circuit. if a pin is not controlled by the pio controller, the state of the pin is defined by the peripheral. in all cases, the level on the pin can be read in the register pio_pdsr. interrupts each parallel i/o can be programmed to generate an interrupt when a level change occurs. this is controlled by the pio_ier and pio_idr registers which enable/disable the i/o interrupt by setting/clearing the corresponding bit in pio_imr. when a change in level occurs, the corresponding bit in pio_isr is set depending on whether the pin is used as a pio or a peripheral, and whether it is defined as input or output. if the corre- sponding interrupt in pio_imr is enabled, the pio interrupt is asserted. when pio_isr is read, the register is automatically cleared.
86 at91c140 6069a?atarm?05/04 i/o line control figure 22. i/o line block diagram pad pio_osr 1 0 1 0 pio_psr pio_odsr 0 1 pio_psr event detection pio_pdsr pio_isr pio_imr peripheral output enable peripheral output peripheral input pioirq pad output enable pad output pad input
87 at91c140 6069a?atarm?05/04 parallel i/o controller (pio) user interface each individual i/o is associated with a bit position in the parallel i/o user interface registers. each of these registers is 32 bits wide. if a parallel i/o line is not defined, writing to the corresponding bits has no effect. undefined bits read as zero. notes: 1. the reset value of this register depends on the level of the external pins at reset. 2. this register is cleared at reset. however, the first read of the register can give a value not equal to zero if any changes have occurred on any pins between the reset and the read. table 24. pio controller memory map offset register name description access reset value 0x00 pio_per pio enable register write-only ? 0x04 pio_pdr pio disable register write-only ? 0x08 pio_psr pio status register read-only ? 0x0c ? reserved ? ? 0x10 pio_oer output enable register write-only ? 0x14 pio_odr output disable register write-only ? 0x18 pio_osr output status register read-only 0x0 0x1c ? reserved ? ? 0x20 ? reserved ? ? 0x24 ? reserved ? ? 0x28 ? reserved ? 0x0 0x2c ? reserved ? ? 0x30 pio_sodr set output data register write-only ? 0x34 pio_codr clear output data register write-only ? 0x38 pio_odsr output data status register read-only 0x0 0x3c pio_pdsr (1) pin data status register read-only see note 1 0x40 pio_ier interrupt enable register write-only ? 0x44 pio_idr interrupt disable register write-only ? 0x48 pio_imr interrupt mask register read-only ? 0x4c pio_isr (2) interrupt status register read-only see note 2
88 at91c140 6069a?atarm?05/04 pio enable register register name: pio_per access type: write-only this register is used to enable indivi dual pins to be controlled by the pio controller instead of the associated peripheral. when the pio is enabled, the associated peripheral (if any) is held at logic zero. 1 = enables the pio to control the corresponding pin (disables peripheral control of the pin). 0 = no effect. pio disable register register name: pio_pdr access type: write-only this register is used to disable pio control of individual pins. when the pio control is disabled, the normal peripheral func- tion is enabled on the corresponding pin. 1 = disables pio control (enables peripheral control) on the corresponding pin. 0 = no effect. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0
89 at91c140 6069a?atarm?05/04 pio status register register name: pio_psr access type: read-only this register indicates which pins are enabled for pio control. this register is updated when pio lines are enabled or disabled. 1 = pio is active on the corresponding line (peripheral is inactive). 0 = pio is inactive on the corresponding line (peripheral is active). pio output enable register register name: pio_oer access type: write-only this register is used to enable pio output drivers. if the pin is driven by a peripheral, there is no effect on the pin but the information is stored. the register is programmed as follows: 1 = enables the pio output on the corresponding pin. 0 = no effect. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0
90 at91c140 6069a?atarm?05/04 pio output disable register register name: pio_odr access type: write-only this register is used to disable pio output drivers. if the pin is driven by the peripheral, there is no effect on the pin, but the information is stored. the register is programmed as follows: 1 = disables the pio output on the corresponding pin. 0 = no effect. pio output status register register name: pio_osr access type: read-only this register shows the pio pin control (output enable) status which is programmed in pio_oer and pio odr. the defined value is effective only if the pin is controlled by the pio. the register reads as follows: 1 = the corresponding pio is output on this line. 0 = the corresponding pio is input on this line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0
91 at91c140 6069a?atarm?05/04 pio set output data register register name: pio_sodr access type: write-only this register is used to set pio output data. it affects the pin only if the corresponding pio output line is enabled and if th e pin is controlled by the pio. otherwise, the information is stored. 1 = pio output data on the corresponding pin is set. 0 = no effect. pio clear output data register register name: pio_codr access type: write-only this register is used to clear pio output data. it affects the pin only if the corresponding pio output line is enabled and if the pin is controlled by the pio. otherwise, the information is stored. 1 = pio output data on the corresponding pin is cleared. 0 = no effect. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0
92 at91c140 6069a?atarm?05/04 pio output data status register register name: pio_odsr access type: read-only this register shows the output data status which is programmed in pio_sodr or pio_codr. the defined value is effec- tive only if the pin is controlled by the pio controller and only if the pin is defined as an output. 1 = the output data for the corresponding line is programmed to 1. 0 = the output data for the corresponding line is programmed to 0. pio pin data status register register name: pio_pdsr access type: read-only this register shows the state of the physical pin of the chip. the pin values are always valid, regardless of whether the pins are enabled as pio, peripheral, input or output. the register reads as follows: 1 = the corresponding pin is at logic 1. 0 = the corresponding pin is at logic 0. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0
93 at91c140 6069a?atarm?05/04 pio interrupt enable register register name: pio_ier access type: write-only this register is used to enable pio interrupts on the corresponding pin. it has an effect whether pio is enabled or not. 1 = enables an interrupt when a change of logic level is detected on the corresponding pin. 0 = no effect. pio interrupt disable register register name: pio_idr access type: write-only this register is used to disable pio interrupts on the corresponding pin. it has an effect whether the pio is enabled or not. 1 = disables the interrupt on the corresponding pin. logic level changes are still detected. 0 = no effect. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0
94 at91c140 6069a?atarm?05/04 pio interrupt mask register register name: pio_imr access type: read-only this register shows which pins have interrupts enabled. it is updated when interrupts are enabled or disabled by writing to pio_ier or pio_idr. 1 = interrupt is enabled on the corresponding pin. 0 = interrupt is not enabled on the corresponding pin. pio interrupt status register register name: pio_isr access type: read-only this register indicates for each pin when a logic value change has been detected (rising or falling edge). this is valid whether the pio is selected for the pin or not and whether the pin is an input or an output. the register is reset to zero following a read and at reset. 1 = at least one input change has been detected on the corresponding pin since the register was last read. 0 = no input change has been detected on the corresponding pin since the register was last read. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 7 6 5 4 3 2 1 0 p7 p6 p5 p4 p3 p2 p1 p0
95 at91c140 6069a?atarm?05/04 universal asynchronous receiver transmitter (uart) the at91c140 provides two identical full-duplex universal asynchronous receiver transmitters, uart a and uart b. these peripherals sit on the apb bus but are also connected to the asb bus (and hence external memory) via a dedicated pdc. the main features are: programmable baud rate generator parity, framing and overrun error detection line break generation and detection automatic echo, local loopback and remote loopback channel modes interrupt generation two dedicated peripheral data controller channels 6-, 7- and 8-bit character length modem control signals block diagram figure 23. uart block diagram peripheral data controller receive channel transmit channel control logic interrupt control baud rate generator receiver transmitter peripheral bridge arm asb apb uart interrupt aclk aclk/8 rxd txd sck uart baud rate clock pio modem control nrts ncts nri ndsr ndtr ndcd
96 at91c140 6069a?atarm?05/04 pin description each uart channel has external signals as defined in table 25. baud rate generator the baud rate generator provides the bit period clock (the baud rate clock) to both the receiver and the transmitter. the baud rate generator can select between external and internal clock sources. the external clock source is sck. the internal clock sources can be either the arm clock (aclk) or the arm clock divided by 8 (aclk/8). note: in all cases, if an external clock is used, the duration of each of its levels must be longer than the system clock (aclk) period. the external clock frequency must be at least 2.5 times lower than the system clock. the selected clock is divided by 16 times the value (cd) written in us_brgr (baud rate generator register). if us_brgr is set to 0, the baud rate clock is disabled. table 25. uart pins signal name description type sck uart serial clock. can be configured as input or output. see us_mr i/o txd transmit serial data output rxd receive serial data input nrts request to send output ncts clear to send input ndtr data terminal ready output ndsr data set ready input ndcd data carrier detect input nri ring indicator input baud rate = selected clock 16 x cd table 26. clock generator table with crystal frequency of 16 mhz required baud rate (bps) cd actual cd actual baud rate (bps) error (bps) % error 9600 260.42 260 9615.385 15,38 0.16 19200 130.21 130 19230.77 30.77 0.16 38400 65.10 65 38461.54 61.54 0.16 57600 43.41 43 58139.53 539.53 0.94 115200 21.70 22 113636.40 -1163.64 -1.36
97 at91c140 6069a?atarm?05/04 figure 24. baud rate generator receiver operations the uart detects the start of a received character by sampling the rxd signal until it detects a valid start bit. a low level (space) on rxd is interpreted as a valid start bit if it is detected for more than seven cycles of the sampling clock, which is 16 times the baud rate. hence, a space which is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver con- tinues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the rxd at the theoreti- cal mid-point of each bit. it is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the sampling point is eight cycles (0.5-bit periods) after the start of the bit. the first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. figure 25. start bit detection figure 26. character reception receiver ready when a complete character is received, it is transferred to the us_rhr and the rxrdy status bit in us_csr is set. if us_rhr has not been read since the last transfer, the ovre status bit in us_csr is set. 0 1 aclk aclk/8 clk 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 usclks [0] 16 x baud r ate clock rxd true start detection d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd true start detection sampling parity bit stop b it e xample: 8-bit, parity enabled 1 stop 1-bit period 0.5-bit periods
98 at91c140 6069a?atarm?05/04 parity error each time a character is received, the receiver calculates the parity of the received data bits in accordance with the field par in us_mr. it then compares the result with the received parity bit. if different, the parity error bit pare in us_csr is set. framing error if a character is received with a stop bit at low level and with at least one data bit at high level, a framing error is generated. this sets frame in us_csr. time-out this function allows an idle condition on the rxd line to be detected. the maximum delay for which the uart should wait for a new character to arrive while the rxd line is inactive (high level) is programmed in us_rtor. when this register is set to 0, no time- out is detected. otherwise, the receiver waits for a first character and then initializes a counter which is decremented at each bit period and reloaded at each byte reception. when the counter reaches 0, the timeout bit in us_csr is set. the user can restart the wait for a first character with th e sttto (start time-out) bit in us_cr. calculation of time-out duration: transmitter start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the falling edge of the serial clock. the number of data bits is selected in the chrl field in us_mr. the parity bit is set according to the par field in us_mr. the number of stop bits is selected in the nbstop field in us_mr. when a character is written to us_thr, it is transferred to the shift register as soon as it is empty. when the transfer occurs, the txrdy bit in us_csr is set until a new char- acter is written to us_thr. if the transmit shift register and us_thr are both empty, the txempty bit in us_csr is set. figure 27. character transmission time-guard the time-guard function allows the transmitter to insert an idle state on the txd line between two characters. the duration of the idle state is programmed in us_ttgr. when this register is set to zero, no time-guard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in us_ttgr. channel modes the uart can be programmed to operate in three different test modes using the field chmode in us_mr. duration value 4 bit period = d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock idle state duration between two characters = time-guard value x bit period
99 at91c140 6069a?atarm?05/04 automatic echo mode allows bit-by-bit re-transmission. when a bit is received on the rxd line, it is sent to the txd line. programming the transmitter has no effect. local loopback mode allows the transmitted characters to be received. txd and rxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the rxd pin level has no effect and the txd pin is held high, as in idle state. remote loopback mode directly connects t he rxd pin to the txd pin. the transmitter and the receiver are disabled and have no effect. this mode allows bit-by-bit re- transmission. figure 28. channel modes peripheral data controller each uart channel is closely connected to a corresponding peripheral data controller channel. one is dedicated to the receiver, the other is dedicated to the transmitter. the pdc channel is programmed using us _tpr and us_tcr for the transmitter and us_rpr and us_rcr for the receiver. the status of the pdc is given in us_csr by the endtx bit for the transmitter and by the endrx bit for the receiver. the pointer registers us_tpr and us_rpr are used to store the address of the trans- mit or receive buffers. the counter registers us_tcr and us_rcr are used to store the size of these buffers. the receiver data transfer is triggered by the rxrdy bit and the transmitter data trans- fer is triggered by txrdy. when a transfer is performed, the counter is decremented and the pointer is incremented. when the counter reaches 0, the status bit is set receiver transmitter disabled rx d txd receiver transmitter disabled rx d txd v dd disabled receiver transmitter disabled rx d txd disabled automatic echo local loopback r emote loopback v dd
100 at91c140 6069a?atarm?05/04 (endrx for the receiver, endtx for the transmitter in us_csr) and can be pro- grammed to generate an interrupt. transfers are then disabled until a new non-zero counter value is programmed. modem control and status signals ncts: clear to send when low, this indicates that the modem or data set is ready to exchange data. the ncts signal is a modem status input; its conditions can be tested by the cpu reading bit 4 (cts) of the modem status register. bit 4 is the complement of the ncts signal. bit 0 (dcts) of the modem status register indicates whether the ncts input has changed state since the previous read of the modem status register. ncts has no effect on the transmitter. ndcd: data carrier detect when low, this indicates that the data carrier has been detected by the modem or data set. the ndcd signal is a modem status input; its condition can be tested by the cpu reading bit 7 (dcd) of the modem status register. bit 7 is the complement of the ndcd signal. bit 3 (ddcd) of the modem status register indicates whether the ndcd input pin has changed since the previous reading of the modem status register. ndcd has no effect on the receiver. ndsr: data set ready when low, this informs the modem or data set that the uart is ready to communicate. the ndsr signal is a modem status input; its condition can be tested by the cpu read- ing bit 5 (dsr) of the modem status register. bit 5 is the complement of the ndsr signal. bit 1 (ddsr of the modem status register) indicates whether the ndsr input has changed state since the previous read of the modem status register. ndtr: data terminal ready when low, this informs the modem or data set that the uart is ready to communicate. the ndtr output signal can be set to active low by programming bit 0 (dtr) of the modem control register to a high level. a master reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. nri: ring indicator when low, this indicates that a tel ephone ringing signal has been received by the modem or data set. the nri signal is a modem status input; its condition can be tested by the cpu reading bit 6 (ri) of the modem status register. bit 6 is the complement of the nri signal. bit 2 (teri) of the modem status register indicates whether the nri input signal has changed from a low to a hi gh state since the previous read of the modem status register. nrts: request to send when low, this informs the modem or data set that the uart is ready to exchange data. the nrts output signal can be set to an active low by programming bit 1 (rts) of the modem control register. a master reset operation sets this signal to its inactive (high) state.
101 at91c140 6069a?atarm?05/04 universal asynchronous receiver/transmitter (uart) user interface table 27. uart memory map offset register name description access reset value 0x00 us_cr control register write-only ? 0x04 us_mr mode register read/write 0 0x08 us_ier interrupt enable register write-only ? 0x0c us_idr interrupt disable register write-only ? 0x10 us_imr interrupt mask register read-only 0 0x14 us_csr channel status register read-only 0x18 0x18 us_rhr receiver holding register read-only 0 0x1c us_thr transmitter holding register write-only ? 0x20 us_brgr baud rate generator register read/write 0 0x24 us_rtor receiver time-out register read/write 0 0x28 us_ttgr transmitter time-guard register read/write 0 0x2c ? reserved ? ? 0x30 us_rpr receive pointer register read/write 0 0x34 us_rcr receive counter register read/write 0 0x38 us_tpr transmit pointer register read/write 0 0x3c us_tcr transmit counter register read/write 0 0x40 us_mc modem control register write-only ? 0x44 us_ms modem status register read-only
102 at91c140 6069a?atarm?05/04 uart control register name: us_cr access type: write-only rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset. rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset. rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. txen: transmitter enable 0 = no effect. 1 = the transmitter is enabled if txdis is 0. txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame, ovre and rxbrk in the us_csr. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? rststa 7 6 5 4 3 2 1 0 txdis txen rxdis rxen rsttx rstrx ? ?
103 at91c140 6069a?atarm?05/04 uart mode register name: us_mr access type: read/write usclks: clock selection chrl: character length par: parity type nbstop: number of stop bits 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 chmode nbstop pa r ? 7 6 5 4 3 2 1 0 chrl usclks ? ? ? ? usclks selected clock 00aclk 01aclk/8 1 x external (sck) chrl character length 00five bits 01six bits 1 0 seven bits 1 1 eight bits pa r parity type 000even parity 0 0 1 odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 10xno parity nbstop 00 1 stop bit 01 1.5 stop bits 10 2 stop bits 11 reserved
104 at91c140 6069a?atarm?05/04 chmode: channel mode chmode mode description 0 0 normal mode the uart channel operates as an rx/tx uart. 0 1 automatic echo receiver data input is connected to txd pin. 1 0 local loopback transmitter output signal is connected to receiver input signal. 1 1 remote loopback rxd pin is internally connected to txd pin.
105 at91c140 6069a?atarm?05/04 uart interrupt enable register name: us_ier access type: write-only rxrdy: enable rxrdy interrupt txrdy: enable txrdy interrupt endrx: enable end of receive transfer interrupt endtx: enable end of transmit transfer interrupt ovre: enable overrun error interrupt frame: enable framing error interrupt pare: enable parity error interrupt txempty: enable txempty interrupt dmsi: delta modem interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? dmsi txempty ? 7 6 5 4 3 2 1 0 pa r e frame ovre endtx endrx ? txrdy rxrdy
106 at91c140 6069a?atarm?05/04 uart interrupt disable register name: us_idr access type: write-only rxrdy: disable rxrdy interrupt txrdy: disable txrdy interrupt endrx: disable end of receive transfer interrupt endtx: disable end of transmit transfer interrupt ovre: disable overrun error interrupt frame: disable framing error interrupt pare: disable parity error interrupt txempty: disable txempty interrupt dmsi: disable delta modem interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? dmsi txempty ? 7 6 5 4 3 2 1 0 pa r e frame ovre endtx endrx ? txrdy rxrdy
107 at91c140 6069a?atarm?05/04 uart interrupt mask register name: us_imr access type: read-only rxrdy: rxrdy interrupt mask txrdy: txrdy interrupt mask endrx: end of receive transfer interrupt mask endtx: end of transmit transfer interrupt mask ovre: overrun error interrupt mask frame: framing error interrupt mask pare: parity error interrupt mask txempty: txempty interrupt mask dmsi: delta modem status indication interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? dmsi txempty ? 7 6 5 4 3 2 1 0 pa r e frame ovre endtx endrx rxbrk ? rxrdy
108 at91c140 6069a?atarm?05/04 uart channel status register name: us_csr access type: read-only rxrdy: receiver ready 0 = no complete character has been received since the last read of the us_rhr or the receiver is disabled. 1 = at least one complete character has been received and the us_rhr has not yet been read. txrdy: transmitter ready 0 = us_thr contains a character waiting to be transferred to the transmit shift register. 1 = us_thr is empty and there is no break request pending tsr availability. equal to zero when the uart is disabled or at reset. transmitter enable command (in us_cr) sets this bit to one. endrx: end-of-receive transfer 0 = the end-of-transfer signal from the pdc channel dedicated to the receiver is inactive. 1 = the end-of-transfer signal from the pdc channel dedicated to the receiver is active. endtx: end-of-transmit transfer 0 = the end-of-transfer signal from the pdc channel dedicated to the transmitter is inactive. 1 = the end-of-transfer signal from the pdc channel dedicated to the transmitter is active. ovre: overrun error 0 = no byte has been transferred from the receive shift regi ster to the us_rhr when rxrdy was asserted since the last reset status bits command. 1 = at least one byte has been transferred from the receive shift register to the us_rhr when rxrdy was asserted since the last reset status bits command. frame: framing error 0 = no stop bit has been detected low since the last reset status bits command. 1 = at least one stop bit has been detected low since the last reset status bits command. pare: parity error 1 = at least one parity bit has been detected false (or a parity bi t high in multi-drop mode) since the last reset status bit? command. 0 = no parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bits command. txempty: transmitter empty 0 = there are characters in either us_thr or the transmit shift register or a break is being transmitted. 1 = there are no characters in us_thr and the transmit shift register and break is not active. equal to zero when the uart is disabled or at reset. transmitter enable command (in us_cr) sets this bit to one. dmsi: delta modem status indication interrupt 0 = no effect. 1 = there has been a change in the modem status delta bits since the last reset status bits command. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? dmsi txempty ? 7 6 5 4 3 2 1 0 pa r e frame ovre endtx endrx ? txrdy rxrdy
109 at91c140 6069a?atarm?05/04 uart receiver holding register name: us_rhr access type: read-only rxchr: received character last character received if rxrdy is set. when number of data bits is less than eight, the bits are right-aligned. uart transmitter holding register name: us_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. when number of data bits is less than eight, the bits are right-aligned. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 rxchr 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 txchr
110 at91c140 6069a?atarm?05/04 uart baud rate ge nerator register name: us_brgr access type: read/write cd: clock divisor this register has no effect if synchronous mode is selected with an external clock. uart receive pointer register name: us_rpr access type: read/write rxptr: receive pointer rxptr must be loaded with the address of the receive buffer. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 cd 7 6 5 4 3 2 1 0 cd cd effect 0 disables clock 1 clock divisor bypass 2 to 65535 baud rate = selected clock/(16 x cd) 31 30 29 28 27 26 25 24 rxptr 23 22 21 20 19 18 17 16 rxptr 15 14 13 12 11 10 9 8 rxptr 7 6 5 4 3 2 1 0 rxptr
111 at91c140 6069a?atarm?05/04 uart receive c ounter register name: us_rcr access type: read/write reset value: 0x0 rxctr: receive counter rxctr must be loaded with the size of the receive buffer. 0 =stop peripheral data transfer dedicated to the receiver. 1 - 65535: start peripheral data transfer if rxrdy is active. uart transmit pointer register name: us_tpr access type: read/write reset value: 0x0 txptr: transmit pointer txptr must be loaded with the address of the transmit buffer. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 rxctr 7 6 5 4 3 2 1 0 rxctr 31 30 29 28 27 26 25 24 txptr 23 22 21 20 19 18 17 16 txptr 15 14 13 12 11 10 9 8 txptr 7 6 5 4 3 2 1 0 txptr
112 at91c140 6069a?atarm?05/04 uart transmit counter register name: us_tcr access type: read/write reset value: 0x0 txctr: transmit counter txctr must be loaded with the size of the transmit buffer. 0 =stop peripheral data transfer dedicated to the transmitter. 1 - 65535: start peripheral data transfer if txrdy is active. modem control register register name: us_mc access type: write-only reset value: undefined this register controls the interface with the modem or data set (or a peripheral device emulating a modem). the contents of the control register are indicated below. dtr: data terminal ready this bit controls the ndtr output. when bit 0 is set to a logic 1, the ndtr output is forced to a logic 0. when bit 0 is reset to a logic 0, the ndtr output is forced to a logic 1. the ndtr output of the uart can be applied to an eia inverting line driver to obtain proper polarity input at the succeed- ing modem or data set. rts: request to send this bit controls the nrts output. bit 1 affects the nrts output in a manner identical to that described above for bit 0. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 txctr 7 6 5 4 3 2 1 0 txctr 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? rts dtr
113 at91c140 6069a?atarm?05/04 modem status register register name: us_ms access type: read-only this register provides the current state of the control lines from the modem (or peripheral device) to the cpu. in addition to this current-state information, four bits of the modem status register provide change information. these bits are set to a logic 1 whenever a control input from the modem changes state. they are reset to logic 0 whenever the cpu reads the modem status register. dcts: delta clear to send bit 0 indicates that the ncts input to the chip has changed state since the last time it was read by the cpu. ddsr: delta data set ready bit 1 indicates that the ndsr input to the chip has changed state since the last time it was read by the cpu. teri: trailing edge ring indicator bit 2 indicates that the nri input to the chip has changed from a low to a high state. ddcd: delta data carrier detect bit 3 indicates that the ndcd input has changed state. note that whenever bit 0, 1, 2, or 3 is set to logic 1, a modem status interrupt is generated. this is reflected in the modem status register. cts: clear to send this bit is the complement of the clear to send (ncts) input. dsr: data set ready this bit is the complement of the data set ready (ndsr) input. ri: ring indicator this bit is the complement of the ring indicator (nri) input. dcd: data carrier detect this bit is the complement of the data carrier detect (ndcd) input. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 dcd ri dsr cts ddcd teri ddsr dcts
114 at91c140 6069a?atarm?05/04 timer/counter (tc) the at91c140 features a timer/counter block that includes three identical 16-bit timer/counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval mea- surement, pulse generation, delay timing and pulse-width modulation. each timer/counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals that can be configured by the user. each channel drives an internal interrupt signal that can be programmed to generate proces- sor interrupts via the aic. the timer/counter block has two global registers which act upon all three tc channels. the block control register allows the three channels to be started simultaneously with the same instruction. the block mode regist er defines the external clock inputs for each timer/counter channel, allowing them to be chained.
115 at91c140 6069a?atarm?05/04 block diagram figure 29. timer/counter block diagram signal name description timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 sync parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int int int tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 advanced interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer/counter block tioa tiob tioa tiob tioa tiob sync sync aclk/2 aclk/8 aclk/32 aclk/128 aclk/1024 table 28. timer counter signal description channel signal description type xc0, xc1, xc2 external clock inputs i tioa capture mode: general-purpose input waveform mode: general-purpose output i o tiob capture mode: general-purpose input waveform mode: general-purpose input/output i o int interrupt signal output o sync synchronization input signal i
116 at91c140 6069a?atarm?05/04 note: after a hardware reset, the timer/counter block pins are controlled by the pio controller. they must be configured to be c on- trolled by the peripheral before being used. description the three timer/counter channels are independent and identical in operation. counter each timer/counter channel is organized around a 16-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and the covfs bit in tc_sr (status register) is set. the current value of the counter is accessible in real time by reading tc_cv. the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. clock selection at block level, input clock signals of each channel can either be connected to the exter- nal inputs tclk0, tclk1 or tclk2, or be connected to the configurable i/o signals tioa0, tioa1 or tioa2 for chaining by programming the tc_bmr (block mode). each channel can independently select an inter nal or external clock source for its counter: internal clock signals: aclk/2, aclk/8, aclk/32, aclk/128, aclk/1024 external clock signals: xc0, xc1 or xc2 the selected clock can be inverted with the clki bit in tc_cmr (channel mode). this allows counting on the opposite edges of the clock. the burst function allows the clock to be validated when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). note: in all cases, if an external clock is used, the duration of each of its levels must be longer than the system clock (aclk) period. the external clock frequency must be at least 2.5 times lower than the system clock (aclk). block signal tclk0, tclk1, tclk2 external clock inputs i tioa0 tioa signal for channel 0 i/o tiob0 tiob signal for channel 0 i/o tioa1 tioa signal for channel 1 i/o tiob1 tiob signal for channel 1 i/o tioa2 tioa signal for channel 2 i/o tiob2 tiob signal for channel 2 i/o table 28. timer counter signal description
117 at91c140 6069a?atarm?05/04 figure 30. clock selection clock control the clock of each counter can be controlled in two different ways: it can be enabled/dis- abled and started/stopped. 1. the clock can be enabled or disabled by the user with the clken and the clk- dis commands in the control register. in capture mode, it can be disabled by an rb load event if ldbdis is set to 1 in tc_cmr. in waveform mode, it can be dis- abled by an rc compare event if cpcdis is set to 1 in tc_cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re-enable the clock. when the clock is enabled, the clksta bit is set in the status register. 2. the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode (ldbstop = 1 in tc_cmr) or a rc compare event in waveform mode (cpcstop = 1 in tc_cmr). the start and the stop commands have an effect only if the clock is enabled. timer/counter operating modes each timer/counter channel can operate independently in two different modes: 1. capture mode allows measurement on signals 2. waveform mode allows wave generation the timer/counter operating mode is programmed with the wave bit in the tc mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. aclk/2 aclk/8 aclk/32 aclk/128 aclk/1024 xc0 xc1 xc2 clks clki burst 1 selecte d clock
118 at91c140 6069a?atarm?05/04 figure 31. clock control trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. the following triggers are common to both modes: 1. software trigger: each channel has a software trigger, available by setting swtrg in tc_ccr. 2. sync: each channel has a synchronization signal, sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all chan- nels are asserted simultaneously by writing tc_bcr (block control) with sync set. 3. compare rc trigger: rc is implemented in each channel and can provide a trig- ger when the counter value matches the rc value if cpctrg is set in tc_cmr. the timer/counter channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed on one of the following signals: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in tc_cmr. if an external trigger is used, the duration of the pulses must be longer than the system clock (aclk) period in order to be detected. whatever the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value may not read zero just after a trigger, especially when a low-frequency signal is selected as the clock. qs r s r q clksta clken clkdis stop event disab le even t counter clock s elected clock trigger
119 at91c140 6069a?atarm?05/04 capture operating mode this mode is entered by clearing the wave parameter in tc_cmr (channel mode register). capture mode allows the tc channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on tioa and tiob signals which are inputs. figure 32 shows the configuration of the tc channel when programmed in capture mode. capture registers a and b (ra and rb) registers a and b are used as capture registers; thus, they can be loaded with the counter value when a programmable event occurs on the tioa signal. the parameter ldra in tc_cmr defines the tioa edge for the loading of register a, and the parameter ldrb defines the tioa edge for the loading of register b. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded since the last trigger or the last loading of rb. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in tc_sr (status register). in this case, the old value is overwritten. trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trigger can be defined. bit abetrg in tc_cmr selects input signal tioa or tiob as an external trigger. parameter etrgedg defines the edge (rising, falling or both) detected to generate an external trigger. if etrgedg = 0 (none), the external trigger is disabled. status register the following bits in the status register are significant in capture operating mode. cpcs: rc compare status there has been an rc compare match at least once since the last read of the status. covfs: counter overflow status the counter has attempted to count past $ffff since the last read of the status. lovrs: load overrun status ra or rb has been loaded at least twice without any read of the corresponding reg- ister since the last read of the status. ldras: load ra status ra has been loaded at least once without any read since the last read of the status. ldrbs: load rb status rb has been loaded at least once without any read since the last read of the status. etrgs: external trigger status an external trigger on tioa or tiob has been detected since the last read of the status.
120 at91c140 6069a?atarm?05/04 figure 32. capture mode waveform operating mode this mode is entered by setting the wave parameter in tc_cmr (channel mode register). waveform operating mode allows the tc channel to generate 1 or 2 pwm signals with the same frequency and independently programmable duty cycles, or to generate differ- ent types of one-shot or repetitive pulses. in this mode, tioa is configured as output and tiob is defined as output if it is not used as an external event (eevt parameter in tc_cmr). figure 33 on page 123 shows the configuration of the tc channel when programmed in waveform operating mode. compare register a, b and c (ra, rb, and rc) in waveform operating mode, ra, rb and rc are all used as compare registers. ra compare is used to control the tioa output. rb compare is used to control the tiob (if configured as output). rc compare can be programmed to control tioa and/or tiob outputs. rc compare can also stop the counter clock (cpcstop = 1 in tc_cmr) and/or dis- able the counter clock (cpcdis = 1 in tc_cmr). aclk/2 aclk/8 aclk/32 aclk/128 aclk/1024 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg tc_imr trig ldrbs ldras etrgs tc_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel
121 at91c140 6069a?atarm?05/04 as in capture mode, rc compare can also generate a trigger if cpctrg = 1. a trigger resets the counter so rc can control the period of pwm waveforms. external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the parameter eevt in tc_cmr selects the external trigger. the parameter eevt- edg defines the trigger edge for each of the possible external triggers (rising, falling or both). if eevtedg is cleared (none), no external event is defined. if tiob is defined as an external event signal (eevt = 0), tiob is no longer used as output and the tc channel can only generate a waveform on tioa. when an external event is defined, it can be used as a trigger by setting bit enetrg in tc_cmr. as in capture mode, the sync signal, the software trigger and the rc compare trigger are also available as triggers. output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defined as output (not as an external event). the following events control tioa and tiob: software trigger, external event and rc compare. ra compare controls tioa and rb compare controls tiob. each of these events can be programmed to set, clear or toggle the output as defined in the corre- sponding parameter in tc_cmr. table 29 and table 30 show which parameter in tc_cmr is used to define the effect of each event. if two or more events occur at the same time, the priority level is defined as follows: 1. software trigger 2. external event 3. rc compare 4. ra or rb compare table 29. tioa events parameter tioa event aswtrg software trigger aeevt external event acpc rc compare acpa ra compare table 30. tiob events parameter tiob event bswtrg software trigger beevt external event bcpc rc compare bcpb rb compare
122 at91c140 6069a?atarm?05/04 status the following bits in the status register are significant in waveform mode: cpas: ra compare status there has been a ra compare match at least once since the last read of the status cpbs: rb compare status there has been a rb compare match at least once since the last read of the status cpcs: rc compare status there has been a rc compare match at least once since the last read of the status covfs: counter overflow counter has attempted to count past $ffff since the last read of the status etrgs: external trigger external trigger has been detected since the last read of the status
123 at91c140 6069a?atarm?05/04 figure 33. waveform mode aclk/2 aclk/8 aclk/32 aclk/128 aclk/1024 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop 16-bit counter eevt eevtedg sync swtrg enetrg cpctrg tc_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel
124 at91c140 6069a?atarm?05/04 timer/counter (tc) user interface tc_bcr (block control register) and tc_bmr (block mode register) control the whole tc block. tc channels are con- trolled by the registers listed in table 32. the offset of each of the channel registers in table 32 is in relation to the offs et of the corresponding channel as specified in table 31. note: 1. read only if wave = 0. table 31. tc global memory map offset register name channel/register access reset value 0x00 tc channel 0 see table 32 0x40 tc channel 1 see table 32 0x80 tc channel 2 see table 32 0xc0 tc_bcr tc block control register write-only ? 0xc4 tc_bmr tc block mode register read/write 0 table 32. tc channel memory map offset register name description access reset value 0x00 tc_ccr channel control register write-only ? 0x04 tc_cmr channel mode register read/write 0 0x08 reserved ? 0x0c reserved ? 0x10 tc_cvr counter value register read/write 0 0x14 tc_ra register a read/write (1) 0 0x18 tc_rb register b read/write (1) 0 0x1c tc_rc register c read/write 0 0x20 tc_sr status register read-only ? 0x24 tc_ier interrupt enable register write-only ? 0x28 tc_idr interrupt disable register write-only ? 0x2c tc_imr interrupt mask register read-only 0
125 at91c140 6069a?atarm?05/04 tc block control register register name: tc_bcr access type: write-only sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? sync
126 at91c140 6069a?atarm?05/04 tc block mode register register name: tc_bmr access type: read/write tc0xc0s: external clock signal 0 selection tc1xc1s: external clock signal 1 selection tc2xc2s: external clock signal 2 selection 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? tc2xc2s tc1xc1s tc0xc0s tc0xc0s signal connected to xc0 00tclk0 01none 10tioa1 11tioa2 tc1xc1s signal connected to xc1 00tclk1 0 1 none 10tioa0 11tioa2 tc2xc2s signal connected to xc2 00tclk2 0 1 none 10tioa0 11tioa1
127 at91c140 6069a?atarm?05/04 tc channel control register register name: tc_ccr access type: write-only clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and clock is started. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? ? ? ? swtrg clkdis clken
128 at91c140 6069a?atarm?05/04 tc channel mode re gister: capture mode register name: tc_cmr access type: read/write tcclks: clock selection clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. burst: burst signal selection ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. ldbdis: counter clock disable with rb loading 0 = counter clock is not disabled when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ldrb ldra 15 14 13 12 11 10 9 8 wave cpctrg ? ? ? abetrg etrgedg 7 6 5 4 3 2 1 0 ldbdis ldbstop burst clki tcclks tcclks clock selected 000aclk/2 001aclk/8 010aclk/32 0 1 1 aclk/128 1 0 0 aclk/1024 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
129 at91c140 6069a?atarm?05/04 etrgedg: external trigger edge selection abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. wave 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ldra: ra loading selection ldrb: rb loading selection etrgedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ldra edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa ldrb edge 00none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa
130 at91c140 6069a?atarm?05/04 tc channel mode regi ster: waveform mode register name: tc_cmr access type: read/write tcclks: clock selection clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. burst: burst signal selection cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. cpcdis: counter clock disable with rc compare 0 = counter clock is not disabled when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave cpctrg ? enetrg eevt eevtedg 7 6 5 4 3 2 1 0 cpcdis cpcstop burst clki tcclks tcclks clock selected 000aclk/2 001aclk/8 010aclk/32 0 1 1 aclk/128 1 0 0 aclk/1024 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
131 at91c140 6069a?atarm?05/04 eevtedg: external event edge selection eevt: external event selection note: if tiob is chosen as the external event signal, it is configured as an input and no longer generates waveforms. enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. wave 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. acpa: ra compare effect on tioa acpc: rc compare effect on tioa eevtedg edge 00none 0 1 rising edge 1 0 falling edge 1 1 each edge eevt signal selected as external event tiob direction 0 0 tiob input (1) 0 1 xc0 output 1 0 xc1 output 1 1 xc2 output acpa effect 0 0 none 01set 10clear 11toggle acpc effect 00none 01set 1 0 clear 1 1 toggle
132 at91c140 6069a?atarm?05/04 aeevt: external event effect on tioa aswtrg: software trigger effect on tioa bcpb: rb compare effect on tiob bcpc: rc compare effect on tiob beevt: external event effect on tiob aeevt effect 00none 01set 10clear 11toggle aswtrg effect 00none 01set 10clear 11toggle bcpb effect 00none 01set 10clear 11toggle bcpc effect 00none 01set 10clear 1 1 toggle beevt effect 00none 01set 10clear 1 1 toggle
133 at91c140 6069a?atarm?05/04 bswtrg: software trigger effect on tiob tc counter value register register name: tc_cvr access type: read-only cv: counter value cv contains the counter value in real-time. bswtrg effect 00none 01set 1 0 clear 1 1 toggle 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 cv 7 6 5 4 3 2 1 0 cv
134 at91c140 6069a?atarm?05/04 tc register a register name: tc_ra access type: read-only if wave = 0, read/write if wave = 1 ra: register a ra contains the register a value in real-time. tc register b register name: tc_rb access type: read-only if wave = 0, read/write if wave = 1 rb: register b rb contains the register b value in real-time. tc register c register name: tc_rc access type: read/write rc: register c rc contains the register c value in real-time. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ra 7 6 5 4 3 2 1 0 ra 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 rb 7 6 5 4 3 2 1 0 rb 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 rc 7 6 5 4 3 2 1 0 rc
135 at91c140 6069a?atarm?05/04 tc status register register name: tc_sr access type: read-only covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the sta- tus register if wave = 0. cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register if wave = 1. cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register if wave = 1. cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ldras: ra loading status 0 = ra load has not occurred since the last read of the status register or wave = 1. 1 = ra load has occurred since the last read of the status register, if wave = 0. ldrbs: rb loading status 0 = rb load has not occurred since the last read of the status register or wave = 1. 1 = rb load has occurred since the last read of the status register if wave = 0. etrgs: external trigger status 0 = external trigger has not occurred since the last read of the status register. 1 = external trigger has occurred since the last read of the status register. clksta: clock enabling status 0 = clock is disabled. 1 = clock is enabled. mtioa: tioa mirror 0 = tioa is low. if wave = 0, then tioa pin is low. if wave = 1, then tioa is driven low. 1 = tioa is high. if wave = 0, then tioa pin is high. if wave = 1, then tioa is driven high. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? mtiob mtioa clksta 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
136 at91c140 6069a?atarm?05/04 mtiob: tiob mirror 0 = tiob is low. if wave = 0, then tiob pin is low. if wave = 1, then tiob is driven low. 1 = tiob is high. if wave = 0, then tiob pin is high. if wave = 1, then tiob is driven high. tc interrupt enable register register name: tc_ier access type: write-only covfs: counter overflow lovrs: load overrun cpas: ra compare cpbs: rb compare cpcs: rc compare ldras: ra loading ldrbs: rb loading etrgs: external trigger 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
137 at91c140 6069a?atarm?05/04 tc interrupt disable register register name: tc_idr access type: write-only covfs: counter overflow lovrs: load overrun cpas: ra compare cpbs: rb compare cpcs: rc compare ldras: ra loading ldrbs: rb loading etrgs: external trigger 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
138 at91c140 6069a?atarm?05/04 tc interrupt mask register register name: tc_imr access type: read-only covfs: counter overflow lovrs: load overrun cpas: ra compare cpbs: rb compare cpcs: rc compare ldras: ra loading ldrbs: rb loading etrgs: external trigger 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
139 at91c140 6069a?atarm?05/04 serial peripheral interface (spi) the at91c140 embeds a serial peripheral interface featuring: four chip selects with external decoder support allowing communication with up to 15 peripherals serial memories, such as dataflash and 3-wire eeproms serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors external co-processors master or slave serial peripheral bus interface 8- to 16-bit programmable data length per chip select programmable phase and polarity per chip select programmable transfer delays between consecutive transfers and between clock and data per chip select programmable delay between consecutive transfers selectable mode fault detection connection to pdc channel capabilities optimizes data transfers one channel for the receiver, one channel for the transmitter overview the serial peripheral interface (spi) circuit is a synchronous serial data link that pro- vides communication with external devices in master or slave mode. it also allows communication between processors if an external processor is connected to the system. the serial peripheral interface is a shift register that serially transmits data bits to other spis. during a data transfer, one spi system acts as the ?master?' that controls the data flow, while the other system acts as the ?slave'' that has data shifted into and out of it by the master. different cpus can take turn bei ng masters (multiple master protocol ver- sus single master protocol, where one cpu is always the master while all of the others are always slaves), and one master may simultaneously shift data into multiple slaves. however, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asserts its nss signal. if multiple slave devices exist, the master generates a separate slave select signal for each slave (npcs). the spi system consists of two data lines and two control lines: master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. serial clock (spck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. slave select (nss): this control line allows slaves to be turned on and off by hardware.
140 at91c140 6069a?atarm?05/04 block diagram figure 34. block diagram spi interface interrupt control pio pdc apb bridge ack spi interrupt spck miso mosi npcs0/ns s npcs1 npcs2 ack/32 npcs3 asb apb
141 at91c140 6069a?atarm?05/04 connections figure 35. application block diagram: single master/multiple slave implementation pin name list master mode operations when configured in master mode, the serial peripheral interface controls data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select(s) to the slave(s) and the serial clock (spck). after enabling the spi, a data transfer begins when the core writes to the spi_tdr (transmit data register). transmit and receive buffers maintain the data flow at a constant rate with a reduced requirement for high-priority interrupt servic ing. when new data is available in the table 33. i/o lines description pin name pin description type mode comments miso master in slave out i/o master slave serial data input to spi serial data output from spi mosi master out slave in i/o master slave serial data output from spi serial data input to spi spck serial clock i/o master slave clock output from spi clock input to spi npcs1-npcs3 peripheral chip selects input master select peripherals npcs0/nss peripheral chip select/slave select i/o master master slave output: selects peripheral input: low causes mode fault input: chip select for spi spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3
142 at91c140 6069a?atarm?05/04 spi_tdr, the spi continues to transfer data. if the spi_rdr (receive data register) has not been read before new data is received, the overrun error (ovres) flag is set. note: as long as this flag is set, no data is loaded in the spi_rdr. the user has to read the status register to clear it. the delay between the activation of the chip select and the start of the data transfer (dlybs), as well as the delay between each data transfer (dlybct), can be pro- grammed for each of the four external chip selects. all data transfer characteristics, including the two timing values, are programmed in registers spi_csr0 to spi_csr3 (chip select registers). in master mode, the peripheral selection can be defined in two different ways: fixed peripheral select: spi exchanges data with only one peripheral variable peripheral select: data can be exchanged with more than one peripheral figure 39 and figure 40 show the operation of the spi in master mode. for details con- cerning the flag and control bits in these diagrams, see ?spi chip select register? on page 157. fixed peripheral select this mode is used for transferring memory blocks without the extra overhead in the transmit data register to determine the peripheral. fixed peripheral select is activated by se tting bit ps to zero in spi_mr (mode regis- ter). the peripheral is defined by the pcs field in spi_mr. this option is only available when the spi is programmed in master mode. variable peripheral select variable peripheral select is activated by setting the ps bit to one. the pcs field in spi_tdr is used to select the destination peripheral. the data transfer characteristics are changed when the selected peripheral changes, depending on the associated chip select register. the pcs field in the spi_mr has no effect. this option is available only when the spi is programmed in master mode. chip selects the chip select lines are driven by the spi only if it is programmed in master mode. these lines are used to select the destination peripheral. the pcsdec field in spi_mr (mode register) selects one to four peripherals (pcsdec = 0) or up to 15 peripherals (pcsdec = 1). if variable peripheral select is active, the chip select signals are defined for each trans- fer in the pcs field in spi_tdr. chip select signals can thus be defined independently for each transfer. if fixed peripheral select is active, chip select signals are defined for all transfers by the field pcs in spi_mr. if a transfer with a new peripheral is necessary, the software must wait until the current transfer is completed, then change the value of pcs in spi_mr before writing new data in spi_tdr. the value on the npcs pins at the end of each transfer can be read in the spi_rdr (receive data register). by default, all npcs signals are high (equal to one) before and after each transfer. mode fault detection a mode fault is detected when the spi is programmed in master mode and a low level is driven by an external master on the npcs[0]/nss signal.
143 at91c140 6069a?atarm?05/04 when a mode fault is detected, the modf bit in the spi_sr is set until the spi_sr is read and the spi is disabled until re-enabled by bit spien in the spi_cr (control register). by default, mode fault detection is enabled. it is disabled by setting the modfdis bit in the spi mode register.
144 at91c140 6069a?atarm?05/04 master mode flow diagram figure 36. master mode flow diagram spi enable tdre ps 1 0 0 1 1 1 0 same peripheral new peripheral npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ps npcs = 0xf delay dlybcs spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) fixed peripheral variable peripheral fixed peripheral variable peripheral delay dlybct 0
145 at91c140 6069a?atarm?05/04 master mode block diagram figure 37. master mode block diagram s p i e n s serializer spi_mr(div32) ack ack/32 spck clock generator spi_csrx[15:0] s r q spi_mr(ps) pcs spi_rdr miso s pi_mr(pcs) spidis spien spi_mr(mstr) spi_sr mosi npcs3 npcs2 npcs1 npcs0 lsb msb spck spi master clock rd pcs spi_tdr td m o d f t d r e r d r f o v r e 0 1 spi_ier spi_idr spi_imr spi interrupt 0 1
146 at91c140 6069a?atarm?05/04 spi slave mode in slave mode, the spi waits for nss to go active low before receiving the serial clock from an external master. in slave mode, cpol, ncpha and bits fiel ds of spi_csr0 are used to define the transfer characteristics. the other chip select registers are not used in slave mode. figure 38. slave mode block diagram data transfers four modes are used for data transfers. these modes correspond to combinations of a pair of parameters called clock polarity (cpol) and clock phase (cpha) that determine the edges of the clock signal on which the data are driven and sampled. each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. thus a master/slave pair must use the same parameter s r q t d r e r d r f o v r e s p i e n s serializer spck spidis spien spi_ier spi_idr spi_imr spi_sr miso lsb msb nss mosi spi_rdr rd spi_tdr td spi interrupt
147 at91c140 6069a?atarm?05/04 pair values to communicate. if multiple slaves are used and fixed in different configura- tions, the master must reconfigure itself each time it needs to communicate with a different slave. table 34 shows the four modes and corresponding parameter settings. figure 39 and figure 40 show examples of data transfers. figure 39. spi transfer format (ncpha = 1, 8 bits per transfer table 34. spi bus protocol mode spi mode cpol cpha 000 101 210 311 spck (cpol=0) spck (cpol=1) 1 234 5 67 mosi (from master) miso (from slave) nss (to slave) s pck cycle (for reference) 8 msb msb lsb lsb 6 6 6 5 5 4 4 3 3 2 2 1 1 * * not defined, but normally msb of previous character received.
148 at91c140 6069a?atarm?05/04 figure 40. spi transfer format (ncpha = 0, 8 bits per transfer) clock generation in master mode, the spi master clock is either clock or fdiv, as defined by the div32 field of spi_mr. the spi baud rate clock is generated by dividing the spi master clock by a value between 4 and 510. the divisor is defined in the scbr field in each chip select register. the transfer speed can thus be defined independently for each chip select signal. cpol and ncpha in the chip select registers define the clock/data relationship between master and slave devices. cpol defines the inactive value of the spck. ncpha defines which edge causes data to change and which edge causes data to be captured. in slave mode, the input clock low and high pulse duration must be longer than two sys- tem clock (clock) periods. spck (cpol=0) spck (cpol=1) 1 234 5 67 mosi (from master) miso (from slave) nss (to slave) s pck cycle (for reference) 8 msb msb lsb lsb 6 6 6 5 5 4 4 3 3 2 2 1 1 * not defined but normally lsb of previous character transmitted. *
149 at91c140 6069a?atarm?05/04 serial peripheral interface (spi) user interface table 35. spi memory map offset register register name access reset 0x00 control register spi_cr write-only --- 0x04 mode register spi_mr read/write 0x0 0x08 receive data register spi_rdr read-only 0x0 0x0c transmit data register spi_tdr write-only --- 0x10 status register spi_sr read-only 0x000000f0 0x14 interrupt enable register spi_ier write-only --- 0x18 interrupt disable register spi_idr write-only --- 0x1c interrupt mask register spi_imr read-only 0x0 0x20 receive pointer register spi_rpr read/write 0x0 0x24 receive counter register spi_rcr read/write 0x0 0x28 transmit pointer register spi_tpr read/write 0x0 0x2c transmit counter register spi_tcr read/write 0x0 0x30 chip select register 0 spi_csr0 read/write 0x0 0x34 chip select register 1 spi_csr1 read/write 0x0 0x38 chip select register 2 spi_csr2 read/write 0x0 0x3c chip select register 3 spi_csr3 read/write 0x0
150 at91c140 6069a?atarm?05/04 spi control register name : spi_cr access type: write-only spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. spidis: spi disable 0 = no effect. 1 = disables the spi. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the control register is written, the spi is disabled swrst: spi software reset 0 = no effect. 1 = resets the spi. a software-triggered hardware reset of the spi interface is performed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? ? ? spidis spien
151 at91c140 6069a?atarm?05/04 spi mode register name: spi_mr access type: read/write mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 16 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 16 chip selects according to the following rules: spi_csr0 defines peripheral chip select signals 0 to 3. spi_csr1 defines peripheral chip select signals 4 to 7. spi_csr2 defines peripheral chip select signals 8 to 11. spi_csr3 defines peripheral chip select signals 12 to 15*. *note : t he 16th state corresponds to a state in which all chip selects are inactive. this allows a different clock configuration to be defined by each chip select registe r. div32: clock selection 0 = spi master clock equals ack. 1 = spi master clock equals ack/32. modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. llb: local loopback enable 0 = local loopback path disabled 1 = local loopback path enabled llb controls the local loopback on the data serializer for testing in master mode only. 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ? ? ? ? pcs 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 llb ? ? modfdis div32 pcsdec ps mstr
152 at91c140 6069a?atarm?05/04 pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs dlybcs: delay between chip selects this field defines the delay from npcs inactive to the activation of another npcs. the dlybcs time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or equal to six, six spi master clock periods will be inserted by default. otherwise, the following equation determines the delay: npcs_to_sck_delay = dlybcs * spi_master_clock_period
153 at91c140 6069a?atarm?05/04 spi receive data register name: spi_rdr access type: read-only rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. pcs: peripheral chip select in master mode only, these bits indicate the value on the np cs pins at the end of a transfer. otherwise, these bits read zero. spi transmit data register name: spi_tdr access type: write-only td: transmit data data to be transmitted by the spi is stored in this register. information to be transmitted must be written to the transmit dat a register in a right-justified format. pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? pcs 15 14 13 12 11 10 9 8 rd 7 6 5 4 3 2 1 0 rd 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? pcs 15 14 13 12 11 10 9 8 td 7 6 5 4 3 2 1 0 td
154 at91c140 6069a?atarm?05/04 spi status register name: spi_sr access type: read-only rdrf: receive data register full 0 = no data has been received since the last read of spi_rdr 1 = data has been received and the received data has been transferred from the serializer to spi_rdr since the last read of spi_rdr. tdre: transmit data register empty 0 = data has been written to spi_tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. modf: mode fault error 0 = no mode fault has been detected since the last read of spi_sr. 1 = a mode fault occurred since the last read of the spi_sr. ovres: overrun error status 0 = no overrun has been detected since the last read of spi_sr. 1 = an overrun has occurred since the last read of spi_sr. an overrun occurs when spi_rdr is loaded at least twice from the serializer since the last read of the spi_rdr. endrx: end of rx buffer 0 = the receive counter register has not reached 0 since the last write in spi_rcr. 1 = the receive counter register has reached 0 since the last write in spi_rcr. endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in spi_tcr. 1 = the transmit counter register has reached 0 since the last write in spi_tcr. spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????spiens 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? endtx endrx ovres modf tdre rdrf
155 at91c140 6069a?atarm?05/04 spi interrupt enable register name: spi_ier access type: write-only rdrf: receive data register full interrupt enable tdre: spi transmit data register empty interrupt enable modf: mode fault error interrupt enable ovres: overrun error interrupt enable endrx: end of receive buffer interrupt enable endtx: end of transmit buffer interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. spi interrupt disable register name: spi_idr access type: write-only rdrf: receive data register full interrupt disable tdre: spi transmit data register empty interrupt disable modf: mode fault error interrupt disable ovres: overrun error interrupt disable endrx: end of receive buffer interrupt disable endtx: end of transmit buffer interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? endtx endrx ovres modf tdre rdrf 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? endtx endrx ovres modf tdre rdrf
156 at91c140 6069a?atarm?05/04 spi interrupt mask register name: spi_imr access type: read-only rdrf: receive data register full interrupt mask tdre: spi transmit data register empty interrupt mask modf: mode fault error interrupt mask ovres: overrun error interrupt mask endrx: end of receive buffer interrupt mask endtx: end of transmit buffer interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? 7 6 5 4 3 2 1 0 ? ? endtx endrx ovres modf tdre rdrf
157 at91c140 6069a?atarm?05/04 spi chip select register name: spi_csr0... spi_csr3 access type: read/write cpol: clock polarity 0 = the inactive state value of sck is logic level zero. 1 = the inactive state value of sck is logic level one. cpol is used to determine the inactive state value of the serial clock (sck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ncpha: clock phase 0 = data is changed on the leading edge of sck and captured on the following edge of sck. 1 = data is captured on the leading edge of sck and changed on the following edge of sck. ncpha determines which edge of sck causes data to c hange and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/data relationship between master and slave devices. bits: bits per transfer the bits field determines the number of data bits transferred. reserved values should not be used. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 7 6 5 4 3 2 1 0 bits ? ? ncpha cpol bits[3:0] bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
158 at91c140 6069a?atarm?05/04 scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the spi master clock (selected between clock and fdiv). the baud rate is selected by writing a value from 2 to 255 in the field scbr. the fol- lowing equation determines the spck baud rate: spck baudrate = spi_master_clock / (2 * scbr) giving scbr a value of zero or one disables the baud rate generator. spck is disabled and assumes its inactive state value. no serial transfers may occur. at reset, baud rate is disabled. dlybs: delay before sck this field defines the delay from npcs valid to the first valid sck transition. when dlybs equals zero, the npcs valid to sck transition is 1/2 the sck clock period. otherwise, the following equation determines the delay: npcs_to_sck_delay = dlybs * spi_master_clock_period dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, a delay of four spi master clock periods are inserted. otherwise, the following equation determines the delay: delay_after_transfer = 32 * dlybct * spi_master_clock_period.
159 at91c140 6069a?atarm?05/04 spi receive pointer register register name: spi_rpr access type: read/write rxptr: receive pointer rxptr must be loaded with the address of the receive buffer. spi receive counter register register name: spi_rcr access type: read/write rxctr: receive counter register rxctr must be loaded with the size of the receive buffer. 0 = stops peripheral data transfer 1 - 65535 = start peripheral data transfer if rdrf is active. 31 30 29 28 27 26 25 24 rxptr 23 22 21 20 19 18 17 16 rxptr 15 14 13 12 11 10 9 8 rxptr 7 6 5 4 3 2 1 0 rxptr 31 30 29 28 27 26 25 24 -- -- -- -- -- -- -- -- 23 22 21 20 19 18 17 16 -- -- -- -- -- -- -- -- 15 14 13 12 11 10 9 8 rxctr 7 6 5 4 3 2 1 0 rxctr
160 at91c140 6069a?atarm?05/04 spi transmit pointer register register name: sp_tpr access type: read/write txptr: transmit pointer register txptr must be loaded with the address of the transmit buffer. spi transmit counter register register name: sp_tcr access type: read/write txctr: transmit counter register txctr must be loaded with the size of the receive buffer. 0 = stops peripheral data transfer 1 - 65535 = start peripheral data transfer if tdre is active. 31 30 29 28 27 26 25 24 txptr 23 22 21 20 19 18 17 16 txptr 15 14 13 12 11 10 9 8 txptr 7 6 5 4 3 2 1 0 txptr 31 30 29 28 27 26 25 24 -- -- -- -- -- -- -- -- 23 22 21 20 19 18 17 16 -- -- -- -- -- -- -- -- 15 14 13 12 11 10 9 8 txctr 7 6 5 4 3 2 1 0 txctr
161 at91c140 6069a?atarm?05/04 ordering information table 36. ordering information ordering reference temp package AT91C140-CI -40c to +85c bga256
162 at91c140 6069a?atarm?05/04 mechanical characteristics and packaging bga packaging information figure 41. at91c140 bga package for bga package data, see table 37 on page 163, ? b
163 at91c140 6069a?atarm?05/04 bga package data . table 37. dimensions (mm) symbol min nom max a1 0.50 0.60 0.70 0.60 0.75 0.90 aaa 0.30 bbb 0.25 ccc 0.35 ddd 0.30 eee 0.15 a 1.92 2.13 2.34 b 0.28 0.32 0.38 d/e 26.8 27.0 27.2 d1/e1 24.0 24.7 e1.27 f8.05 ? b
164 at91c140 6069a?atarm?05/04
i at91c140 6069a?atarm?05/04 table of contents features............................................................................................................ 1 description....................................................................................................... 1 block diagram ................................................................................................. 2 pinout ............................................................................................................... 3 256-ball bga package pinout ......................................................................... 3 mechanical overview of the 256-ball bga package........................................ 5 peripheral multiplexing on pio lines ............................................................ 6 pio controller a multiplexing .......................................................................... 7 pio controller b multiplexing .......................................................................... 8 signal description .......................................................................................... 9 arm7tdmi core ............................................................................................ 12 power supplies .............................................................................................. 12 system controller .......................................................................................... 12 test ................................................................................................................ 12 reset controller ............................................................................................. 12 clock generator ............................................................................................. 13 chip id ........................................................................................................... 13 system controller user interface.................................................................... 14 system mode register................................................................................... 15 system id register ........................................................................................ 16 system clock status register........................................................................ 16 memory controller (mc)................................................................................ 17 architecture .................................................................................................... 17 memory map .................................................................................................. 18 arm asb arbitration...................................................................................... 19 mac asb arbitration...................................................................................... 19 asb-asb bridge arbitration ........................................................................... 19 boot mode...................................................................................................... 20 endianness .................................................................................................... 20 peripherals ..................................................................................................... 21 peripheral registers....................................................................................... 21 peripheral memory map ................................................................................. 22
ii at91c140 6069a?atarm?05/04 peripheral data controller (pdc) ................................................................. 23 pdc overview................................................................................................ 23 pdc channel priority ..................................................................................... 23 boot program ................................................................................................. 24 boot mode...................................................................................................... 24 hardware connection of the dataflash ......................................................... 24 internal boot software.................................................................................... 24 dataflash header details .............................................................................. 25 reserved resources...................................................................................... 25 external bus interface (ebi) ......................................................................... 27 signal multiplexing ........................................................................................ 27 sdram controller (sdramc) ...................................................................... 28 description ..................................................................................................... 28 block diagram................................................................................................ 28 i/o lines description ..................................................................................... 29 application example....................................................................................... 29 sdram device initialization .......................................................................... 31 sdram controller write cycle ...................................................................... 33 sdram controller read cycle ...................................................................... 34 border management ...................................................................................... 35 sdram controller refresh cycles ................................................................ 36 sdram user interface...................................................................................... 37 sdramc mode register ............................................................................... 37 sdramc refresh timer register ................................................................. 38 sdramc configuration register ................................................................... 39 sdramc address register ........................................................................... 40 static memory controller (smc) .................................................................. 41 external memory mapping ............................................................................. 41 pin description ............................................................................................... 41 data bus width .............................................................................................. 41 byte write or byte select mode ..................................................................... 42 read protocols............................................................................................... 42 write protocol................................................................................................. 43 wait states ..................................................................................................... 43 signal waveforms .......................................................................................... 44 smc user interface........................................................................................... 47 smc chip select register ............................................................................. 48 smc memory control register ...................................................................... 49
iii at91c140 6069a?atarm?05/04 ethernet mac (emac)................................................................................... 50 block diagram................................................................................................ 50 media independent interface ........................................................................ 51 transmit/receive operation .......................................................................... 51 dma operations............................................................................................. 53 address checking .......................................................................................... 55 emac user interface ........................................................................................ 57 emac control register.................................................................................. 58 emac mode register .................................................................................... 59 emac status register ................................................................................... 60 emac transmit address register ................................................................. 60 emac transmit control register ................................................................... 61 emac transmit status register .................................................................... 62 emac receive buffer queue pointer register.............................................. 63 emac receive status register ..................................................................... 63 emac interrupt status register..................................................................... 64 emac interrupt enable register .................................................................... 65 emac interrupt disable register ................................................................... 66 emac interrupt mask register ...................................................................... 67 emac phy maintenance register ................................................................ 68 emac hash address high register .............................................................. 69 emac hash address low register ............................................................... 69 emac specific address (1, 2, 3 and 4) high register ................................... 70 emac specific address (1, 2, 3 and 4) low register.................................... 70 emac statistics register block registers ..................................................... 71 advanced interrupt controller (aic) ............................................................ 72 priority controller ........................................................................................... 73 interrupt handling........................................................................................... 73 standard interrupt sequence ......................................................................... 74 fast interrupt.................................................................................................. 75 software interrupt........................................................................................... 75 spurious interrupt........................................................................................... 76 aic user interface............................................................................................. 77 aic source mode register ............................................................................ 78 aic interrupt vector registers ....................................................................... 79 aic fiq vector register ................................................................................ 79 aic interrupt status register ......................................................................... 80 aic interrupt mask register ........................................................................... 80 aic core interrupt status register ................................................................ 81 aic interrupt enable command register....................................................... 81 aic interrupt disable command register ...................................................... 82 aic interrupt clear command register ......................................................... 82 aic interrupt set command register ............................................................ 83 aic end of interrupt command register ....................................................... 83
iv at91c140 6069a?atarm?05/04 aic spurious interrupt vector register .......................................................... 84 parallel i/o controller (pio) .......................................................................... 85 output selection............................................................................................. 85 i/o levels ....................................................................................................... 85 interrupts ........................................................................................................ 85 i/o line control .............................................................................................. 86 parallel i/o controller (pio) user interface .................................................... 87 pio enable register ...................................................................................... 88 pio disable register...................................................................................... 88 pio status register ....................................................................................... 89 pio output enable register........................................................................... 89 pio output disable register .......................................................................... 90 pio output status register............................................................................ 90 pio set output data register ........................................................................ 91 pio clear output data register..................................................................... 91 pio output data status register ................................................................... 92 pio pin data status register......................................................................... 92 pio interrupt enable register ........................................................................ 93 pio interrupt disable register ....................................................................... 93 pio interrupt mask register........................................................................... 94 pio interrupt status register ......................................................................... 94 universal asynchronous receiver transmitter (uart) ............................ 95 block diagram................................................................................................ 95 pin description ............................................................................................... 96 baud rate generator ..................................................................................... 96 receiver operations ...................................................................................... 97 transmitter ..................................................................................................... 98 channel modes .............................................................................................. 98 peripheral data controller.............................................................................. 99 modem control and status signals.............................................................. 100 universal asynchronous receiver/transmitter (uart) user interface .... 101 uart control register ................................................................................ 102 uart mode register ................................................................................... 103 uart interrupt enable register .................................................................. 105 uart interrupt disable register.................................................................. 106 uart interrupt mask register ..................................................................... 107 uart channel status register ................................................................... 108 uart receiver holding register................................................................. 109 uart transmitter holding register............................................................. 109 uart baud rate generator register .......................................................... 110 uart receive pointer register................................................................... 110 uart receive counter register ................................................................. 111 uart transmit pointer register.................................................................. 111
v at91c140 6069a?atarm?05/04 uart transmit counter register ................................................................ 112 modem control register .............................................................................. 112 modem status register................................................................................ 113 timer/counter (tc)...................................................................................... 114 block diagram.............................................................................................. 115 signal name description.............................................................................. 115 description ................................................................................................... 116 capture operating mode.............................................................................. 119 waveform operating mode .......................................................................... 120 timer/counter (tc) user interface ................................................................ 124 tc block control register............................................................................ 125 tc block mode register .............................................................................. 126 tc channel control register ....................................................................... 127 tc channel mode register: capture mode................................................. 128 tc channel mode register: waveform mode ............................................. 130 tc counter value register .......................................................................... 133 tc register a............................................................................................... 134 tc register b............................................................................................... 134 tc register c .............................................................................................. 134 tc status register....................................................................................... 135 tc interrupt enable register ....................................................................... 136 tc interrupt disable register....................................................................... 137 tc interrupt mask register .......................................................................... 138 serial peripheral interface (spi) ................................................................. 139 overview ...................................................................................................... 139 block diagram.............................................................................................. 140 connections ................................................................................................. 141 pin name list .............................................................................................. 141 master mode operations.............................................................................. 141 spi slave mode ........................................................................................... 146 data transfers ............................................................................................. 146 clock generation ......................................................................................... 148 serial peripheral interface (spi) user interface ........................................... 149 spi control register .................................................................................... 150 spi mode register ....................................................................................... 151 spi receive data register .......................................................................... 153 spi transmit data register ......................................................................... 153 spi status register ...................................................................................... 154 spi interrupt enable register ...................................................................... 155 spi interrupt disable register...................................................................... 155 spi interrupt mask register ......................................................................... 156 spi chip select register.............................................................................. 157 spi receive pointer register....................................................................... 159
vi at91c140 6069a?atarm?05/04 spi receive counter register ..................................................................... 159 spi transmit pointer register...................................................................... 160 spi transmit counter register .................................................................... 160 ordering information...................................................................................... 161 mechanical characteristics and packaging ................................................. 162 bga packaging information ......................................................................... 162 bga package data ...................................................................................... 163 document details ........................................................................................... 164 revision history ........................................................................................... 164 table of contents i
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